Auto-reset ternary latch

Claim 2

An auto-reset ternary latch comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of three potential levels, an output line having applied thereto electrical signals at any one of three potential levels, means connecting said lines for causing the potential of the output to assume and maintain a set value in response to maintenance of the potential of the gate line at an intermediate level, and for causing the potential of the output line to match and maintain any of the three potential levels of the data input line in response to lowering of the potential of the gate line to the lowermost level.

Claim 3

An auto-reset ternary latch as recited in claim 1 and comprising means for maintaining the potential of the output line at its set or matching value when the potential of the gate line is thereafter raised.

Claim 4

An auto-reset ternary latch comprising a gate line, an output line, each of said lines having applied thereto electrical signals at any one of three potential levels, and means connecting said lines for causing the potential of the output line to move up or down one level to an intermediate level and for maintaining the output line potential at said intermediate level in response to lowering of the potential of the gate line from an uppermost level to an intermediate level.

Claim 5

An auto-reset ternary latch comprising a gate line, an output line, each of said lines having applied thereto electrical signals at any one of three potential levels, and means connecting said lines for causing the potential of the output line to move up or down one level to an intermediate level and for maintaining the output line potential at said intermediate level in response to lowering of the potential of the gate line from an uppermost level to an intermediate level.

Claim 6

An auto-reset ternary latch as recited in claim 3 wherein said means comprises: means connecting said lines for maintaining the potential of the output line at its intermediate level as the potential of the gate line is thereafter raised.

Claim 7

An auto-reset ternary latch as recited in claim 4 and comprising: a data input line, said means further comprising means connecting said data input line for causing the potential of the output line to assume and maintain any of the three potential levels of the data input line in response to lowering of the gate line to the lowermost level.

Claim 8

A ternary latch circuit comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of three potential levels, an output line having applied thereto electrical signals at any one of three potential levels, and means connecting said lines and responsive to the attainment by the gate input line of a predetermined potential level for causing the potential of the output line to vary correspondingly with the potential of the data input line as the potential of the data input line goes to any of said first-recited three potential levels.

Claim 9

A ternary latch circuit comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of three potential levels, an output line having applied thereto electrical signals at any one of three potential levels, and means connecting said lines and responsive to the attainment by the gate input line of a predetermined potential level for causing the potential of the output line to vary correspondingly with the potential of the data input line as the potential of the data input line goes to any of said first-recited three potential levels.

Claim 10

A ternary latch circuit as set forth in claim 6 wherein said means is responsive to the lowering of the potential of the gate input line to the lowermost of said second-recited three potential levels.

Claim 11

A ternary latch circuit comprising a first pair of ternary OR gates each having two inputs and one output, a first pair of ternary Interchanger 1 gates each having an input and an output, means connecting the output of each Interchanger 1 gate to an input of a respective one of said OR gates, means connecting the output of each OR gate to the input of a respective one of said Interchanger 1 gates, a second pair of ternary OR gates each having two inputs and one output, a second pair of ternary Interchanger 1 gates each having an input and an output, means connecting the output of each of said second pair of Interchanger 1 gates to the other input of a respective one of said first pair of OR gates, means connecting the output of one of said second pair of Interchanger 1 gates to an input of one of said second pair of OR gates, means connecting the output of the other of said second pair of OR gates to the input of said one of said second pair of Interchanger 1 gates, and means connecting the output of said one of said second pair of OR gates to the input of the other of said second pair of Interchanger 1 gates.

Claim 12

A ternary latch circuit comprising a first pair of ternary OR gates each having two inputs and one output, a first pair of ternary Interchanger 1 gates each having an input and an output, means connecting the output of each Interchanger 1 gate to an input of a respective one of said OR gates, means connecting the output of each OR gate to the input of a respective one of said Interchanger 1 gates, a second pair of ternary OR gates each having two inputs and one output, a second pair of ternary Interchanger 1 gates each having an input and an output, means connecting the output of each of said second pair of Interchanger 1 gates to the other input of a respective one of said first pair of OR gates, means connecting the output of one of said second pair of Interchanger 1 gates to an input of one of said second pair of OR gates, means connecting the output of the other of said second pair of OR gates to the input of said one of said second pair of Interchanger 1 gates, and means connecting the output of said one of said second pair of OR gates to the input of the other of said second pair of Interchanger 1 gates.

Claim 13

A ternary latch circuit as set forth in claim 8 and comprising means for transmitting a data signal to one input of said other of said second pair of OR gates, and means for transmitting a gate signal to the other inputs of each of said second pair of OR gates.

Claim 14

An auto-reset ternary latch comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of three potential levels, an output line having applied thereto electrical signals at any one of three potential levels, means connecting said lines for causing the potential of the output line to assume and maintain a set value in response to maintenance of the potential of the gate line at a first predetermined level, and for causing the potential of the output line to match and maintain any of the three potential levels of the data input line in response to a transition of the potential of the gate line to a second predetermined level.

Claim 15

An auto-reset ternary latch comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of three potential levels, an output line having applied thereto electrical signals at any one of three potential levels, means connecting said lines for causing the potential of the output line to assume and maintain a set value in response to maintenance of the potential of the gate line at a first predetermined level, and for causing the potential of the output line to match and maintain any of the three potential levels of the data input line in response to a transition of the potential of the gate line to a second predetermined level.

Claim 16

An auto-reset ternary latch as recited in claim 10 wherein said means comprises means for maintaining the potential of the output line at its set or matching level when the potential of the gate line is thereafter raised.

Claim 17

A ternary latch circuit comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of said three potential levels, an output line having applied thereto electrical signals at any one of said three potential levels, and means connecting said lines and responsive to the attainment by the gate input line of a predetermined potential level for causing the potential of the output line to assume and maintain the potential of the data input line as the potential of the data input line goes to any of said three potential levels.

Claim 18

A ternary latch circuit comprising a data input line having applied thereto electrical signals at any one of three potential levels, a gate input line having applied thereto electrical signals at any one of said three potential levels, an output line having applied thereto electrical signals at any one of said three potential levels, and means connecting said lines and responsive to the attainment by the gate input line of a predetermined potential level for causing the potential of the output line to assume and maintain the potential of the data input line as the potential of the data input line goes to any of said three potential levels.

Claim 19

A ternary latch circuit as set forth in claim 12 wherein said means is responsive to the lowering of the potential of the gate input line to the lowermost of said three potential levels.