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US5448166A
Expired / Lapsed
US
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Powered testing of mixed conventional/boundary-scan logic
Assignee: Agilent Technologies Inc
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Filing: 1993-11-22
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Granted: 1995-09-05
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Expires: 2013-11-22
Abstract
Abstract A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance "R" from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into "independent" groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation. The response vector reflects which of the nodes has failed, and cartesian coordinate data giving the precise location of any faulty node(s) is returned to user.
Inventors
- 👤 Kenneth P. Parker
- 👤 Kenneth E. Posse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318586
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
336 words
A method of testing a circuit board having (i) a plurality of non-boundary-scan (NBS) devices, each of the NBS devices having a number of device pins for electrically coupling to the circuit board; (ii) a plurality of boundary-scan (BS) devices, each BS device having a number device pins for electrically coupling to the circuit board, a number of receiver circuits coupled to at least some of the device pins, and a number of driver circuits coupled to at least some of the device pins, wherein the receiver and driver circuits are provided on the plurality of BS devices, wherein each of the receiver circuits and driver circuits are serially coupled to form a scan path for providing a serial data stream representing a desired state of the driver circuits and a resulting state of the receiver circuits to a data processor for analysis; (iii) a number of BS nodes wherein each BS node is coupled to both a receiver circuit and a driver circuit, and (iv) a number of NBS nodes that are nodes that are not BS nodes, the method comprising the steps of: providing adjacency data for each of the device pins of the BS and NBS devices on the circuit board to the tester; grouping the NBS nodes into sets of nodes using the adjacency data, each set of nodes comprising all of the NBS nodes that are adjacent one of the BS nodes; grouping the NBS nodes into groups of independent NBS nodes such that no two members of any independent group are adjacent to the same boundary-scan node; applying a first voltage to the BS nodes of the circuit using the BS driver circuits; applying a second voltage to all NBS node in one group of independent NBS nodes; causing the receiver circuits to capture voltages on the device pins that the receiver circuits are coupled to; causing the scan path to provide a first data stream to the data processor; and analyzing the first data stream using the data processor.
Claim 2
Independent Claim
336 words
A method of testing a circuit board having (i) a plurality of non-boundary-scan (NBS) devices, each of the NBS devices having a number of device pins for electrically coupling to the circuit board; (ii) a plurality of boundary-scan (BS) devices, each BS device having a number device pins for electrically coupling to the circuit board, a number of receiver circuits coupled to at least some of the device pins, and a number of driver circuits coupled to at least some of the device pins, wherein the receiver and driver circuits are provided on the plurality of BS devices, wherein each of the receiver circuits and driver circuits are serially coupled to form a scan path for providing a serial data stream representing a desired state of the driver circuits and a resulting state of the receiver circuits to a data processor for analysis; (iii) a number of BS nodes wherein each BS node is coupled to both a receiver circuit and a driver circuit, and (iv) a number of NBS nodes that are nodes that are not BS nodes, the method comprising the steps of: providing adjacency data for each of the device pins of the BS and NBS devices on the circuit board to the tester; grouping the NBS nodes into sets of nodes using the adjacency data, each set of nodes comprising all of the NBS nodes that are adjacent one of the BS nodes; grouping the NBS nodes into groups of independent NBS nodes such that no two members of any independent group are adjacent to the same boundary-scan node; applying a first voltage to the BS nodes of the circuit using the BS driver circuits; applying a second voltage to all NBS node in one group of independent NBS nodes; causing the receiver circuits to capture voltages on the device pins that the receiver circuits are coupled to; causing the scan path to provide a first data stream to the data processor; and analyzing the first data stream using the data processor.
Claim 3
Dependent Claim
29 words
The method of testing of claim 1 wherein the step of providing adjacency data comprises providing two cartesian coordinates for each of the device pins on the circuit board.
Claim 4
Dependent Claim
46 words
The method of testing of claim 2 wherein the step of providing adjacency data further comprises providing a radius R which is a distance corresponding to the maximum expected size of defects on the circuit board and is in the range of one to five millimeters.
Claim 5
Dependent Claim
19 words
The method of testing of claim 1 wherein the step of providing position data comprises providing numerical adjacency data.
Claim 6
Dependent Claim
25 words
The method of testing of claim 1 wherein at least some of the plurality of non-boundary-scan devices are integrated circuits having analog inputs and outputs.
Claim 7
Dependent Claim
21 words
The method of testing of claim 1 wherein at least some of the plurality of non-boundary-scan devices are discrete electronic devices.
Claim 8
Dependent Claim
27 words
The method of testing claim 1 wherein the step of applying a second voltage to at least one NBS node is completed in less than 200 nanoseconds.
Claim 9
Dependent Claim
25 words
The method of testing of claim 7 wherein the step of applying a second voltage to at least one NBS node uses in-circuit overdrive techniques.
References Cited (Backward Citations)
US3870953A
Cited
US4027353A
Cited
US4459693A
Cited
US4588945A
Cited
US4601032A
Cited
US4534028A
Cited
US4879717A
Cited
US4827208A
Cited
US4872169A
Cited
US4857835A
Cited
US4875209A
Cited
US4967142A
Cited
EP0358376A2
Cited
US4963824A
Cited
US4989209A
Cited
EP0400876A2
Cited
US5054024A
Cited
US5132974A
Cited
US5042034A
Cited
US5046034A
Cited
US5070296A
Cited
US5172377A
Cited
US5329533A
Cited
EP0550135A2
Cited
US5270642A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |