US4989209A
Expired / Lapsed
US
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Method and apparatus for testing high pin count integrated circuits
Assignee: NXP USA Inc
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Filing: 1989-03-24
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Granted: 1991-01-29
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Expires: 2009-03-24
Abstract
Abstract An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.
Inventors
- 👤 Hugh W. Littlebury
- 👤 Mavin C. Swapp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:05
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31905
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
281 words
An apparatus for transferring test data and response data between a multi-channel tester and a logic circuit under test, the apparatus capable of operating in one of a plurality of modes, the logic circuit having a plurality of terminals, each terminal of the plurality of terminals is an input or an output depending on internal configuration of the logic circuit, the apparatus comprising: a plurality of segments which are similar to each other, each segment coupled between one test channel of the multi-channel tester and a subset of terminals of the circuit under test, wherein the test channel provides serial stimulus data to the segment and analyzes serial response data from the segment, each segment including a first converter means having a serial input and a plurality of parallel outputs for dividing the serial stimulus data among the subset of terminals when the apparatus is operating in a first of the plurality of modes, a second converter means having a plurality of parallel inputs and a serial output for assembling response data from the subset of terminals to form the serial response data and sending the serial response data to the tester, and a plurality of terminal electronic units which are similar to each other connected to each logic circuit terminal, the terminal electronic units further comprising a latching means to temporarily store the divided stimulus data from the first converter means, a means to force a logic signal on an input logic circuit terminal controlled by the divided stimulus data stored in the latching means, a comparator to compare a response voltage at an output terminal to a reference voltage and output the response data to the second converter means.
Claim 2
Independent Claim
281 words
An apparatus for transferring test data and response data between a multi-channel tester and a logic circuit under test, the apparatus capable of operating in one of a plurality of modes, the logic circuit having a plurality of terminals, each terminal of the plurality of terminals is an input or an output depending on internal configuration of the logic circuit, the apparatus comprising: a plurality of segments which are similar to each other, each segment coupled between one test channel of the multi-channel tester and a subset of terminals of the circuit under test, wherein the test channel provides serial stimulus data to the segment and analyzes serial response data from the segment, each segment including a first converter means having a serial input and a plurality of parallel outputs for dividing the serial stimulus data among the subset of terminals when the apparatus is operating in a first of the plurality of modes, a second converter means having a plurality of parallel inputs and a serial output for assembling response data from the subset of terminals to form the serial response data and sending the serial response data to the tester, and a plurality of terminal electronic units which are similar to each other connected to each logic circuit terminal, the terminal electronic units further comprising a latching means to temporarily store the divided stimulus data from the first converter means, a means to force a logic signal on an input logic circuit terminal controlled by the divided stimulus data stored in the latching means, a comparator to compare a response voltage at an output terminal to a reference voltage and output the response data to the second converter means.
Claim 3
Dependent Claim
107 words
The apparatus of claim 1 wherein each segment further comprises: a first multiplexer used for coupling a precision power supply to one terminal of the subset of terminals, the at least one input multiplexer being controlled by a control signal from the tester; a second multiplexer used for selecting data on one of the subset of terminals and sending the data to a parametric measurement circuit in the tester, the second multiplexer being controlled by the control signal from the tester, whereby when the apparatus is operating in a second of the plurality of modes parametric data is measured from one terminal of the subset of terminals.
Claim 4
Dependent Claim
154 words
The apparatus of claim 1 wherein each segment further comprises: a buffer, having a serial input and a serial output, for conditioning the serial stimulus data from the tester; a switching means coupled to a terminal of the subset of terminals, the switching means being controlled by the tester and activated when the apparatus is in a third mode of the plurality of modes, the switching means capable of disconnecting the terminal from the means to force a logic signal and coupling the terminal to an output of the buffer; a first multiplexer used for directing the serial stimulus data from the test channel to the input of the buffer; and a detector, having a serial input and a serial output, for detecting output data from the logic circuit and sending the serial response signal; the switching means further capable of disconnecting the terminal from the comparator and connecting the terminal to the detector.
Claim 5
Dependent Claim
39 words
The apparatus of claim 1 wherein the means to force a logic signal is further capable of forcing a logic high voltage, a logic low voltage, and a high impedance condition on the terminal of the circuit under test.
Claim 6
Dependent Claim
21 words
The apparatus of claim 1 wherein the subset of terminals comprises sixteen terminals, and each segment comprises sixteen terminal electronics units.
Claim 7
Dependent Claim
18 words
The apparatus of claim 1 wherein the first converter means and the second converter means comprise shift registers.
Claim 8
Dependent Claim
21 words
The apparatus of claim 5 further comprising sixty four electronic segments, the apparatus being capable of testing circuits with 1024 terminals.
Claim 9
Dependent Claim
45 words
The apparatus of claim 3 wherein the apparatus is operated in the first mode for a plurality of cycles in order to bring the logic circuit to a known state, and subsequently operated in the third mode to evaluate the logic circuit's speed of operation.
Claim 10
Independent Claim
132 words
An apparatus for interfacing between a tester and an integrated circuit comprising: a first shift register having a serial input and a plurality of parallel outputs, the serial input coupled to one test channel; a plurality of binary latches, each latch coupled to one of the parallel outputs of the first shift register; a plurality of switches, controlled by the binary latches, used to couple a logic reference signal to each terminal of the integrated circuit; a plurality of comparators, each comparator coupled to one terminal of the integrated circuit, used to detect a response voltage at the terminal; a second shift register having a plurality of parallel inputs and a serial output, each of the parallel inputs coupled to one comparator, and the serial output coupled to the one test channel.
Claim 11
Independent Claim
132 words
An apparatus for interfacing between a tester and an integrated circuit comprising: a first shift register having a serial input and a plurality of parallel outputs, the serial input coupled to one test channel; a plurality of binary latches, each latch coupled to one of the parallel outputs of the first shift register; a plurality of switches, controlled by the binary latches, used to couple a logic reference signal to each terminal of the integrated circuit; a plurality of comparators, each comparator coupled to one terminal of the integrated circuit, used to detect a response voltage at the terminal; a second shift register having a plurality of parallel inputs and a serial output, each of the parallel inputs coupled to one comparator, and the serial output coupled to the one test channel.
Claim 12
Dependent Claim
24 words
The apparatus of claim 9 wherein the logic reference signal comprises a logic high state, a logic low state, and a high impedance state.
Claim 13
Dependent Claim
76 words
The apparatus of claim 10 further comprising two first shift registers, each first shift register Coupled to the test channel and having a plurality of parallel outputs, each first shift register being associated with a set of the binary latches which control the plurality of switches, wherein one of the first shift registers transfers data indicating a logic high stimulus, and the other of the first shift registers transfers stimulus data indicating a high impedance stimulus.
Claim 14
Independent Claim
113 words
A method of coupling an integrated circuit having a plurality of terminals to a multi-channel tester, each channel providing a serial stimulus signal and analyzing a serial response signal, comprising the steps of: converting the serial stimulus signal to a parallel stimulus signal; storing the parallel stimulus signal in a binary latch, wherein the binary latch has one output associated with each terminal of the integrated circuit; generating a logic signal which is a function of the output of the binary latch; and detecting a response signal from each terminal of the plurality of terminals; assembling the response signals from a set of the plurality of terminals to form the serial response signal.
Claim 15
Independent Claim
113 words
A method of coupling an integrated circuit having a plurality of terminals to a multi-channel tester, each channel providing a serial stimulus signal and analyzing a serial response signal, comprising the steps of: converting the serial stimulus signal to a parallel stimulus signal; storing the parallel stimulus signal in a binary latch, wherein the binary latch has one output associated with each terminal of the integrated circuit; generating a logic signal which is a function of the output of the binary latch; and detecting a response signal from each terminal of the plurality of terminals; assembling the response signals from a set of the plurality of terminals to form the serial response signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |