Patent US3012474A successfully refreshed from Google Patents.
EP0400876A2
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EP
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Method and apparatus for testing circuit boards
Assignee: AT&T Inc
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Filing: 1990-05-23
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Granted: —
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Expires: 2010-05-23
Abstract
Abstract A test system (10) is associated with a chain of circuits (12) on a circuit board (13) for testing the interconnections (11) linking the circuits in the chain as well as for testing the interconnections linking them to those on other boards. The test system includes a controller (22) for generating a test signal and for capturing a response signal generated by the associated chain of circuits in response to the test signal. The controller (22) also generates a flow control signal which controls a network (24) that routes the test signals from the controller, or from a first other test system, to the associated chain of circuits (12). In accordance with the flow control signal, the network (24) also serves to route the response signal from the associated chain of circuits (12) to the controller (22) or to a second other test system. By selectively routing the test and response signals, the network (24) in each test system (10) allows individual testing of each associated chain of circuits or, alternatively, permits the chains of circuits on several boards to be effectively interconnected for testing.
Inventors
- 👤 Najmi T. Jarwala
- 👤 Chi W. Yau
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/3185; G01R31/318533; G01R31/318558
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
129 words
A system for testing circuit boards, characterised by controller means (22) for generating a test data signal for input to a circuit board and for capturing a response signal generated by the board following receipt of the test data signal, said controller means also generating a flow control signal for controlling the passage of signals between the circuit board and the controller means; and network means (24) coupled between the controller means and the circuit board and responsive to the flow control signal for selectively passing the test data signal from the controller means, or from another test system associated with another circuit board, to the circuit board and for selectively passing the response signal from the circuit board either to the test system or to another test system.
Claim 2
Independent Claim
129 words
A system for testing circuit boards, characterised by controller means (22) for generating a test data signal for input to a circuit board and for capturing a response signal generated by the board following receipt of the test data signal, said controller means also generating a flow control signal for controlling the passage of signals between the circuit board and the controller means; and network means (24) coupled between the controller means and the circuit board and responsive to the flow control signal for selectively passing the test data signal from the controller means, or from another test system associated with another circuit board, to the circuit board and for selectively passing the response signal from the circuit board either to the test system or to another test system.
Claim 3
Dependent Claim
36 words
The system according to claim 1, characterised in that said network means (24) further serves to selectively pass the test data signal from the controller means, or from another test system, to a further test system.
Claim 4
Dependent Claim
218 words
The system according to claim 2, characterised in that said network means comprises: a first multiplexer (28) having a first input coupled to receive the test data signal from the controller means and having a second input coupled to receive the test data signal from the first other test system, the multiplexer being responsive to the flow control signal from the controller means for selectively passing the signal at one of its first and second inputs to the circuit board; a second multiplexer (34) having a first input coupled to receive the response signal generated by the circuit board, and a second input coupled to receive the test data signal generated by the first other test system, the second multiplexer being responsive to the flow control signal from the controller means for selectively passing the signal received at its first and second inputs to the controller means for capture thereby; and a third multiplexer (32) having a first input coupled to receive the test data signal from the first other test system, and a second input coupled to receive the response signal from the circuit board, the third multiplexer being responsive to the flow control signal from the controller means for selectively passing the signal received at its first and second inputs to the second other test system.
Claim 5
Dependent Claim
30 words
The system according to claim 3, characterised in that a bypass data register (36) is interposed between the first other test system and the first input of the third multiplexer.
Claim 6
Dependent Claim
47 words
The system according to claim 1, characterised in that the controller means comprises: a test data generator (60) for generating test data signals; a test data receiver (66) for receiving response signals; and means for providing control information (62) to the test generator and test data receiver.
Claim 7
Dependent Claim
91 words
The system according to claim 5, characterised in that the test data generator comprises: a first memory (70) for storing a predetermined set of signals; a second memory (78) containing information descriptive of the circuit board; an automatic test pattern (85) generator for generating a test data signal in accordance with at least one algorithm; and a multiplexer (76) responsive to the information contained in the first memory for selectively passing test data from a separate one of the first memory and the automatic test pattern generator to the circuit board.
Claim 8
Dependent Claim
159 words
The system according to claim 6, characterised in that the automatic test pattern generator comprises: a first module (86) for generating a test data signal consisting of a successive set of vectors, which, when arrayed in matrix form, exhibits a diagonal of all ones; a second module (88) for generating a test data signal consisting of successive vectors which increase monotonically; a third module (90) for generating a test data signal consisting of successive vectors each of whose bits are pseudorandomly generated; a fourth module (92) for generating a test data signal consisting of successive vectors whose bits are all ones; and a multiplexer (116) having a first, second, third and fourth input supplied with the test data signal produced by a separate one of the first, second, third and fourth modules, respectively, the multiplexer being responsive to an externally supplied mode select signal for selectively passing the signal at a separate one of its inputs to its output.
Claim 9
Independent Claim
56 words
A method for testing circuit boards, characterised by generating at least one test signal; generating a flow control signal for controlling the passage of test signals to a board and the passage of response signals therefrom; and selectively routing test signals to, and response signals from, each circuit board in response to the flow control signals.
Claim 10
Independent Claim
56 words
A method for testing circuit boards, characterised by generating at least one test signal; generating a flow control signal for controlling the passage of test signals to a board and the passage of response signals therefrom; and selectively routing test signals to, and response signals from, each circuit board in response to the flow control signals.
Claim 11
Dependent Claim
38 words
The method according to claim 8, characterised in that the test signals and response signals are routed such that a test signal is independently routed to, and a response signal is independently routed from, each circuit board (12).
Claim 12
Dependent Claim
37 words
The method according to claim 8, characterised in that the test and response signals are routed such that the response signal of each circuit board (12) is routed as the test signal to a successive circuit board.
Claim 13
Independent Claim
142 words
A method for generating at least one test vector whose bits, when successively shifted into a chain of serially connected elements, cause no conflicts between elements in potential conflict with each other, the method comprising the steps of: storing at least one test vector whose bits are selected such that, when each bit is shifted into an element in potential conflict with another, no conflict in fact arises; storing information indicative of which of the serially connected elements is in potential conflict from each other; generating at least one test vector whose bits are determined in accordance with a preselected algorithm; and selectively shifting a bit from a separate one of the stored test vectors and the generated test vector to each successive element in the chain, depending on whether the element is identified as being in potential conflict with another element.
Claim 14
Independent Claim
142 words
A method for generating at least one test vector whose bits, when successively shifted into a chain of serially connected elements, cause no conflicts between elements in potential conflict with each other, the method comprising the steps of: storing at least one test vector whose bits are selected such that, when each bit is shifted into an element in potential conflict with another, no conflict in fact arises; storing information indicative of which of the serially connected elements is in potential conflict from each other; generating at least one test vector whose bits are determined in accordance with a preselected algorithm; and selectively shifting a bit from a separate one of the stored test vectors and the generated test vector to each successive element in the chain, depending on whether the element is identified as being in potential conflict with another element.
References Cited (Backward Citations)
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