Partitioned boundary-scan testing for the reduction of testing-induced damage

Claim 1

A method for reducing testing induced component damage during a boundary-scan interconnect test performed on an electronic circuit, wherein the circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, the method comprising the steps of: (a) selecting, for each boundary-scan net, a designated driver; (b) performing a boundary-scan interconnect shorts sub-test on the circuit using each designated driver to test the circuit for short-circuits occurring between said boundary-scan nets, and discontinuing further testing if a short circuit is found until said short circuit is repaired; and (c) performing a boundary-scan bus wire sub-test after completing said boundary-scan interconnect shorts sub-test to test, for each boundary-scan net having a plurality of drivers, the interconnection between each of said plurality of drivers.

Claim 2

A method for reducing testing induced component damage during a boundary-scan interconnect test performed on an electronic circuit, wherein the circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, the method comprising the steps of: (a) selecting, for each boundary-scan net, a designated driver; (b) performing a boundary-scan interconnect shorts sub-test on the circuit using each designated driver to test the circuit for short-circuits occurring between said boundary-scan nets, and discontinuing further testing if a short circuit is found until said short circuit is repaired; and (c) performing a boundary-scan bus wire sub-test after completing said boundary-scan interconnect shorts sub-test to test, for each boundary-scan net having a plurality of drivers, the interconnection between each of said plurality of drivers.

Claim 10

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit.

Claim 11

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit.

Claim 17

A method for performing boundary-scan interconnect testing of an electronic circuit, wherein the electronic circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, the plurality of independent conductive nets including both single-driver nets and multi-driver nets, said method comprising the steps of: (a) designating a driver on each multi-driver net, each said designated driver to be used to test the interconnectivity of each multi-driver net; (b) performing a boundary-scan interconnect shorts test on said electronic circuit using a diagnostic test pattern which includes a plurality of test vectors and said designated drivers to detect short-circuit faults between said plurality of independent conductive nets; (c) stopping testing and repairing the electronic circuit, if any short-circuit faults are detected in step (b); and (d) performing a boundary-scan bus-wire test to test all other drivers on each multi-driver net for open-circuit faults.

Claim 18

A method for performing boundary-scan interconnect testing of an electronic circuit, wherein the electronic circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, the plurality of independent conductive nets including both single-driver nets and multi-driver nets, said method comprising the steps of: (a) designating a driver on each multi-driver net, each said designated driver to be used to test the interconnectivity of each multi-driver net; (b) performing a boundary-scan interconnect shorts test on said electronic circuit using a diagnostic test pattern which includes a plurality of test vectors and said designated drivers to detect short-circuit faults between said plurality of independent conductive nets; (c) stopping testing and repairing the electronic circuit, if any short-circuit faults are detected in step (b); and (d) performing a boundary-scan bus-wire test to test all other drivers on each multi-driver net for open-circuit faults.

Claim 19

A method for reducing testing induced component damage during a boundary-scan interconnect test performed on an electronic circuit, wherein the circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test to test the circuit for short-circuits occurring between a conventional net and a boundary-scan net; (b) selecting, for each boundary-scan net, a designated driver; (c) performing a boundary-scan interconnect shorts sub-test on the circuit using each designated driver to test the circuit for short-circuits occurring between said boundary-scan nets; (d) performing a boundary-scan bus wire sub-test to test, for each boundary-scan net having a plurality of drivers, the interconnection between each of said plurality of drivers; and (e) performing a boundary-scan in-circuit test to test the electrical connection between a boundary-scan circuit component and a partial boundary-scan net.

Claim 20

A method for reducing testing induced component damage during a boundary-scan interconnect test performed on an electronic circuit, wherein the circuit includes a plurality of integrated circuit chips which are electrically interconnected by a plurality of independent conductive nets, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test to test the circuit for short-circuits occurring between a conventional net and a boundary-scan net; (b) selecting, for each boundary-scan net, a designated driver; (c) performing a boundary-scan interconnect shorts sub-test on the circuit using each designated driver to test the circuit for short-circuits occurring between said boundary-scan nets; (d) performing a boundary-scan bus wire sub-test to test, for each boundary-scan net having a plurality of drivers, the interconnection between each of said plurality of drivers; and (e) performing a boundary-scan in-circuit test to test the electrical connection between a boundary-scan circuit component and a partial boundary-scan net.

Claim 23

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit, said powered shorts boundary-scan sub-test comprises the steps of: (1) selecting a conventional net for test; (2) contacting said conventional net with a tester probe; (3) driving said conventional net to a predetermined logic value using said tester probe; (4) serially scanning a fifth test vector into the circuit through a scanpath; (5) broadcasting said fifth test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (6) capturing said fifth test vector into a plurality of receiving register cells in the circuit; (7) serially scanning said fifth test vector out of the receiving register cells via said scanpath; (8) repeating steps (a)(4) through (a)(7) for a plurality of fifth test vectors; and (9) analyzing said plurality of captured fifth test vectors to diagnose any short-circuit faults occurring between said conventional net and said boundary-scan nets; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit, said boundary-scan interconnect shorts sub-test comprises the steps of: (1) selecting, for each boundary-scan net, a designated driver; (2) serially scanning a test vector into the circuit through a scanpath; (3) broadcasting said test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said test vector out of the receiving register cells via said scanpath; (6) repeating steps (c)(2) through (c)(5) for a plurality of said test vectors; and (7) analyzing said plurality of captured test vectors to diagnose any short-circuit faults occurring between said boundary-scan nets; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers, said boundary-scan bus wire sub-test comprises the steps of: (1) for each boundary-scan net having a plurality of output drivers, selecting a driver to be tested and disabling all other drivers on the boundary-scan net; (2) serially scanning a second test vector into the circuit through a scanpath to test a first logic state of each selected driver; (3) broadcasting said second test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said second test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said second test vector out of the receiving register cells via said scanpath; (6) serially scanning a third test vector into the circuit through a scanpath to test a second logic state of each selected driver; (7) broadcasting said third test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (8) capturing said third test vector into a plurality of receiving register cells in the circuit; (9) serially scanning said third test vector out of the receiving register cells via said scanpath; (10) repeating steps (e)(1) through (e)(9) N times, where N is equal to the largest number of drivers on any one of said boundary-scan nets; and (11) analyzing said plurality of captured third and fourth test vectors to diagnose any open-circuit faults occurring between said multiple drivers of each boundary-scan net; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit, said boundary-scan in-circuit sub-test comprises the steps of: (1) selecting a partial boundary-scan net for test, said partial boundary-scan net including a boundary-scan driver; (2) contacting said partial boundary-scan net with a tester probe; (3) serially scanning a sixth test vector into the circuit through a scanpath; (4) broadcasting said sixth test vector from said boundary-scan driver over said partial boundary-scan net; (5) receiving said sixth test vector at said tester probe; (6) repeating steps (f)(3) through (f)(5) as required; and (7) analyzing said sixth test vectors received at step (5) to diagnose any open-circuit faults occurring in said partial boundary-scan net.

Claim 24

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit, said powered shorts boundary-scan sub-test comprises the steps of: (1) selecting a conventional net for test; (2) contacting said conventional net with a tester probe; (3) driving said conventional net to a predetermined logic value using said tester probe; (4) serially scanning a fifth test vector into the circuit through a scanpath; (5) broadcasting said fifth test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (6) capturing said fifth test vector into a plurality of receiving register cells in the circuit; (7) serially scanning said fifth test vector out of the receiving register cells via said scanpath; (8) repeating steps (a)(4) through (a)(7) for a plurality of fifth test vectors; and (9) analyzing said plurality of captured fifth test vectors to diagnose any short-circuit faults occurring between said conventional net and said boundary-scan nets; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit, said boundary-scan interconnect shorts sub-test comprises the steps of: (1) selecting, for each boundary-scan net, a designated driver; (2) serially scanning a test vector into the circuit through a scanpath; (3) broadcasting said test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said test vector out of the receiving register cells via said scanpath; (6) repeating steps (c)(2) through (c)(5) for a plurality of said test vectors; and (7) analyzing said plurality of captured test vectors to diagnose any short-circuit faults occurring between said boundary-scan nets; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers, said boundary-scan bus wire sub-test comprises the steps of: (1) for each boundary-scan net having a plurality of output drivers, selecting a driver to be tested and disabling all other drivers on the boundary-scan net; (2) serially scanning a second test vector into the circuit through a scanpath to test a first logic state of each selected driver; (3) broadcasting said second test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said second test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said second test vector out of the receiving register cells via said scanpath; (6) serially scanning a third test vector into the circuit through a scanpath to test a second logic state of each selected driver; (7) broadcasting said third test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (8) capturing said third test vector into a plurality of receiving register cells in the circuit; (9) serially scanning said third test vector out of the receiving register cells via said scanpath; (10) repeating steps (e)(1) through (e)(9) N times, where N is equal to the largest number of drivers on any one of said boundary-scan nets; and (11) analyzing said plurality of captured third and fourth test vectors to diagnose any open-circuit faults occurring between said multiple drivers of each boundary-scan net; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit, said boundary-scan in-circuit sub-test comprises the steps of: (1) selecting a partial boundary-scan net for test, said partial boundary-scan net including a boundary-scan driver; (2) contacting said partial boundary-scan net with a tester probe; (3) serially scanning a sixth test vector into the circuit through a scanpath; (4) broadcasting said sixth test vector from said boundary-scan driver over said partial boundary-scan net; (5) receiving said sixth test vector at said tester probe; (6) repeating steps (f)(3) through (f)(5) as required; and (7) analyzing said sixth test vectors received at step (5) to diagnose any open-circuit faults occurring in said partial boundary-scan net.

Claim 25

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit, said powered shorts boundary-scan sub-test comprises the steps of: (1) selecting a conventional net for test; (2) contacting said conventional net with a tester probe; (3) driving said conventional net to a predetermined logic value using said tester probe; (4) serially scanning a fifth test vector into the circuit through a scanpath; (5) broadcasting said fifth test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (6) capturing said fifth test vector into a plurality of receiving register cells in the circuit; (7) serially scanning said fifth test vector out of the receiving register cells via said scanpath; (8) repeating steps (a)(4) through (a)(7) for a plurality of fifth test vectors; and (9) analyzing said plurality of captured fifth test vectors to diagnose any short-circuit faults occurring between said conventional net and said boundary-scan nets; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit, said boundary-scan interconnect shorts sub-test comprises the steps of: (1) selecting, for each boundary-scan net, a designated driver; (2) serially scanning a test vector into the circuit through a scanpath; (3) broadcasting said test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said test vector out of the receiving register cells via said scanpath; (6) repeating steps (c)(2) through (c)(5) for a plurality of said test vectors; and (7) analyzing said plurality of captured test vectors to diagnose any short-circuit faults occurring between said boundary-scan nets; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers, said boundary-scan bus wire sub-test comprises the steps of: (1) for each boundary-scan net having a plurality of output drivers, selecting a driver to be tested and disabling all other drivers on the boundary-scan net; (2) serially scanning a second test vector into the circuit through a scanpath to test a first logic state of each selected driver; (3) broadcasting said second test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said second test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said second test vector out of the receiving register cells via said scanpath; (6) serially scanning a third test vector into the circuit through a scanpath to test a second logic state of each selected driver; (7) broadcasting said third test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (8) capturing said third test vector into a plurality of receiving register cells in the circuit; (9) serially scanning said third test vector out of the receiving register cells via said scanpath; (10) repeating steps (e)(1) through (e)(9) N times, where N is equal to the largest number of drivers on any one of said boundary-scan nets; and (11) analyzing said plurality of captured third and fourth test vectors to diagnose any open-circuit faults occurring between said multiple drivers of each boundary-scan net; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit, said boundary-scan in-circuit sub-test comprises the steps of: (1) selecting a partial boundary-scan net for test, said partial boundary-scan net including a boundary-scan receiver; (2) contacting said partial boundary-scan net with a tester probe; (3) driving a test bit onto said partial boundary-scan net using said tester probe; (4) receiving said test bit at said boundary-scan receiver; (5) repeating steps (f)(3) through (f)(4) as required; and (6) analyzing said test bits received at step (4) to diagnose any open-circuit faults occurring in said partial boundary-scan net.

Claim 26

A method for performing a boundary-scan interconnect test on an electronic circuit, comprising the steps of: (a) performing a powered shorts boundary-scan sub-test on the circuit to detect short-circuit faults occurring between conventional nets and boundary-scan nets in the electronic circuit, said powered shorts boundary-scan sub-test comprises the steps of: (1) selecting a conventional net for test; (2) contacting said conventional net with a tester probe; (3) driving said conventional net to a predetermined logic value using said tester probe; (4) serially scanning a fifth test vector into the circuit through a scanpath; (5) broadcasting said fifth test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (6) capturing said fifth test vector into a plurality of receiving register cells in the circuit; (7) serially scanning said fifth test vector out of the receiving register cells via said scanpath; (8) repeating steps (a)(4) through (a)(7) for a plurality of fifth test vectors; and (9) analyzing said plurality of captured fifth test vectors to diagnose any short-circuit faults occurring between said conventional net and said boundary-scan nets; (b) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (a); (c) performing a boundary-scan interconnect shorts sub-test to detect short-circuit faults occurring between boundary-scan nets in the electronic circuit, said boundary-scan interconnect shorts sub-test comprises the steps of: (1) selecting, for each boundary-scan net, a designated driver; (2) serially scanning a test vector into the circuit through a scanpath; (3) broadcasting said test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said test vector out of the receiving register cells via said scanpath; (6) repeating steps (c)(2) through (c)(5) for a plurality of said test vectors; and (7) analyzing said plurality of captured test vectors to diagnose any short-circuit faults occurring between said boundary-scan nets; (d) stopping testing and repairing the electronic circuit if any short-circuit faults are detected in step (c); (e) performing a boundary-scan bus wire sub-test to detect open-circuit faults occurring in each boundary-scan net having a plurality of drivers, said boundary-scan bus wire sub-test comprises the steps of: (1) for each boundary-scan net having a plurality of output drivers, selecting a driver to be tested and disabling all other drivers on the boundary-scan net; (2) serially scanning a second test vector into the circuit through a scanpath to test a first logic state of each selected driver; (3) broadcasting said second test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (4) capturing said second test vector into a plurality of receiving register cells in the circuit; (5) serially scanning said second test vector out of the receiving register cells via said scanpath; (6) serially scanning a third test vector into the circuit through a scanpath to test a second logic state of each selected driver; (7) broadcasting said third test vector from a plurality of output drivers in the circuit over said boundary-scan nets; (8) capturing said third test vector into a plurality of receiving register cells in the circuit; (9) serially scanning said third test vector out of the receiving register cells via said scanpath; (10) repeating steps (e)(1) through (e)(9) N times, where N is equal to the largest number of drivers on any one of said boundary-scan nets; and (11) analyzing said plurality of captured third and fourth test vectors to diagnose any open-circuit faults occurring between said multiple drivers of each boundary-scan net; and (f) performing a boundary-scan in-circuit sub-test to detect open-circuit faults in each partial boundary-scan net in the electronic circuit, said boundary-scan in-circuit sub-test comprises the steps of: (1) selecting a partial boundary-scan net for test, said partial boundary-scan net including a boundary-scan receiver; (2) contacting said partial boundary-scan net with a tester probe; (3) driving a test bit onto said partial boundary-scan net using said tester probe; (4) receiving said test bit at said boundary-scan receiver; (5) repeating steps (f)(3) through (f)(4) as required; and (6) analyzing said test bits received at step (4) to diagnose any open-circuit faults occurring in said partial boundary-scan net.