Patent US5444366A successfully refreshed from Google Patents.
US5444366A
Expired / Lapsed
US
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Wafer burn-in and test system
Assignee: Texas Instruments Inc
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Filing: 1994-02-04
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Granted: 1995-08-22
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Expires: 2014-02-04
Abstract
Abstract An interconnection system and method of testing and performing burn-in of semiconductor devices prior to separation from the semiconductor wafer on which the devices are formed includes forming interconnection layers of contacts and conductors over the devices and then testing and performing burn-in on the devices. Faulty devices are disconnected from the conductors prior to performing additional test and burn-in. The interconnections are removed prior to separating the device on the wafer, and prior to further possible tests and packaging.
Inventors
- 👤 Anthony M. Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/2856; H; H10; H10P; H10P74/00; G01R31/286; G01R31/2863
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
138 words
An interconnection system for burn-in and testing of semiconductor devices prior to separation from a semiconductor wafer, comprising: a semiconductor wafer having a plurality of semiconductor devices thereon arranged in rows, each semiconductor device having a plurality of bond pads and first and second edges extending in a row direction; a plurality of conductors on the wafer overlaying and insulated from the semiconductor devices, each of the plurality of conductors overlaying the semiconductor devices in a row without extending over the first and second edges of the semiconductor devices in the row; an electrical connection between each of said plurality of conductors and a corresponding bond pad on each of said semiconductor devices in a row; and a plurality of test points on said wafer, each of said plurality of conductors connected to one of said test points.
Claim 2
Dependent Claim
138 words
An interconnection system for burn-in and testing of semiconductor devices prior to separation from a semiconductor wafer, comprising: a semiconductor wafer having a plurality of semiconductor devices thereon arranged in rows, each semiconductor device having a plurality of bond pads and first and second edges extending in a row direction; a plurality of conductors on the wafer overlaying and insulated from the semiconductor devices, each of the plurality of conductors overlaying the semiconductor devices in a row without extending over the first and second edges of the semiconductor devices in the row; an electrical connection between each of said plurality of conductors and a corresponding bond pad on each of said semiconductor devices in a row; and a plurality of test points on said wafer, each of said plurality of conductors connected to one of said test points.
Claim 3
Dependent Claim
35 words
The interconnection system according to claim 1, wherein the connection between each of said plurality of conductors and a corresponding bond pad on each of said semiconductor devices in a row is a fuse link.
Claim 4
Dependent Claim
25 words
The interconnection system of claim 1 in which said electrical connection is a low power carrying conductor which opens when an overload occurs during burn-in.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-21 | 2003-02-20 | 2003-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-21 | 2007-02-20 | 2007-08-22 | $7700.00 | Window Closed / Lapsed |