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US5434094A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of producing a field effect transistor

Assignee: Mitsubishi Electric Corp
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Filing: 1994-04-08
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Granted: 1995-07-18
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Expires: 2014-04-08
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Abstract

Abstract FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.

Inventors

  • 👤 Michihiro Kobiki
  • 👤 Masahiro Yoshida
  • 👤 Takahide Ishikawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 13:34
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10P54/00; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/20; H10W40/00; H10W40/10; H10W42/00; H10W42/121; Y; Y10; Y10S; Y10S148/00; Y10S148/028; Y10S438/00; Y10S438/977

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 238 words
A method of making semiconductor devices comprising: forming at least one active region at the front surface of a semiconductor wafer having opposed front and rear surfaces; depositing at least two electrodes in a predetermined relationship with each other on the front surface of the wafer at the active region; etching at least one via-hole in the wafer from the front surface and extending toward the rear surface adjacent the electrodes at the active region; etching at least one circumferential separation groove outwardly spaced from the active region in the wafer from the front surface and extending toward the rear surface for separating a portion of said wafer as a semiconductor device; depositing a first metallic layer in the at least one via-hole and in the at least one separation groove and on the front surface adjacent the via-hole in contact with one of the electrodes and adjacent the separation groove as a measurement electrode; reducing the thickness of the wafer at the rear surface to expose the first metallic layer; depositing a second metallic layer on the rear surface in electrical communication with the first metallic layer in the via-hole; forming a heat sink on the second metallic layer by plating; and dividing the wafer at the separation groove to form an individual semiconductor device on a heat sink having a metallic protection layer on the lateral walls of the substrate between the front and rear surfaces.
Claim 2
Independent Claim 238 words
A method of making semiconductor devices comprising: forming at least one active region at the front surface of a semiconductor wafer having opposed front and rear surfaces; depositing at least two electrodes in a predetermined relationship with each other on the front surface of the wafer at the active region; etching at least one via-hole in the wafer from the front surface and extending toward the rear surface adjacent the electrodes at the active region; etching at least one circumferential separation groove outwardly spaced from the active region in the wafer from the front surface and extending toward the rear surface for separating a portion of said wafer as a semiconductor device; depositing a first metallic layer in the at least one via-hole and in the at least one separation groove and on the front surface adjacent the via-hole in contact with one of the electrodes and adjacent the separation groove as a measurement electrode; reducing the thickness of the wafer at the rear surface to expose the first metallic layer; depositing a second metallic layer on the rear surface in electrical communication with the first metallic layer in the via-hole; forming a heat sink on the second metallic layer by plating; and dividing the wafer at the separation groove to form an individual semiconductor device on a heat sink having a metallic protection layer on the lateral walls of the substrate between the front and rear surfaces.
Claim 3
Dependent Claim 17 words
The method of claim 1 including forming said active region by implanting impurity ions in the wafer.
Claim 4
Dependent Claim 50 words
The method of claim 1 wherein depositing at least two electrodes comprises forming two electrodes making ohmic contact to the active region of the wafer as source and drain electrodes, respectively, and forming a gate electrode making a Schottky barrier with the wafer interposed between said source and drain electrodes.
Claim 5
Dependent Claim 14 words
The method of claim 1 including etching the via-hole and the separation groove simultaneously.
Claim 6
Dependent Claim 14 words
The method of claim 1 including dry etching the via-hole and the separation groove.
Claim 7
Dependent Claim 14 words
The method of claim 1 including wet etching the via-hole and the separation groove.
Claim 8
Dependent Claim 13 words
The method of claim 1 including depositing gold as the first metallic layer.
Claim 9
Dependent Claim 18 words
The method of claim 1 including reducing the thickness of the wafer by combined mechanical and chemical polishing.
Claim 10
Dependent Claim 18 words
The method of claim 1 including forming the heat sink by plating gold on the second metallic layer.
Claim 11
Dependent Claim 17 words
The method of claim 1 including dividing said wafer by severing the wafer at the separation groove.
Claim 12
Dependent Claim 17 words
The method of claim 1 including dividing said wafer by etching the wafer at the separation groove.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-17 1999-01-16 1999-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-17 2003-01-16 2003-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-17 2007-01-16 2007-07-18 $7700.00 Window Closed / Lapsed

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