EP0188879A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Edge channel FET
Assignee: Eaton Corp
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Filing: 1985-12-04
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Granted: —
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Expires: 2005-12-04
Abstract
Abstract Edge channel FET structural geometry and processing are disclosed. A plurality of mesa stacked horizontal layers are provided including source and drain semiconductor layers (74, 76) separated by an insulator layer (75) and having exposed edges (78, 80) at a generally vertical side (83) of the mesa. A generally vertical semiconductor layer (84) extends along the side of the mesa over the exposed source and drain layer edges and forms a channel (93). A gate layer (91, 92) on the channel controls depletion region spreading in the channel layer to control conduction therethrough between the source and drain layers. Channel length is extremely small, as low as 0.1 micron. Ohmic contacts (87, 90) to the source and drain layers are defined several microns away from the conducting channel, resulting in considerable reduction in fabrication complexity, as well as improved reliability. Fabrication and alignment of the gate to the active channel layer is simplified.
Inventors
- 👤 Joseph Anthony Calviello
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 06:08
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D30/00; H10D30/80; H10D30/87; H10D30/871
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
91 words
A field effect transistor comprising: a plurality of mesa stacked horizontal layers including source (74) and drain (76) semiconductor layers separated by an insulator layer (75) and having exposed edges (78,80) at a generally vertical side of the mesa; . a generally vertical semiconductor layer (84) extending along said side of said mesa over said exposed edges and forming a channel; (93) and a gate electrode laye (91) on said channel layer for controlling depletion region spreading in said channel layer to control conduction therethrough between said source and drain layers.
Claim 2
Dependent Claim
91 words
A field effect transistor comprising: a plurality of mesa stacked horizontal layers including source (74) and drain (76) semiconductor layers separated by an insulator layer (75) and having exposed edges (78,80) at a generally vertical side of the mesa; . a generally vertical semiconductor layer (84) extending along said side of said mesa over said exposed edges and forming a channel; (93) and a gate electrode laye (91) on said channel layer for controlling depletion region spreading in said channel layer to control conduction therethrough between said source and drain layers.
Claim 3
Dependent Claim
43 words
The invention according to claim 1 wherein one (74) of said source and drain layers extends horizontall beyond the other, and comprising laterally offset source (87) and drain (90) electrode layers on the upper surface of respective said source and drain semiconductor layers.
Claim 4
Dependent Claim
35 words
The invention according to claim 2 wherein said source and drain electrode layers are at different vertical heights spaced by the thickness of said insulator layer and the other of said source and drain layers.
Claim 5
Dependent Claim
180 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate; a first generally horizontal semiconductor layer on said substrate providing one of said source and drain; a generally horizontal insulator layer on said first semiconductor layer; a second generally horizontal semiconductor layer on said insulator layer and providing the other of said source and drain; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers; . a third semiconductor layer having a generally vertical section extending along said side of said mesa over said exposed edges of said first and second semiconductor layers and said insulator layer and providing a channel, said third semiconductor layer having a generally horizontal section on said substrate adjacent said first semiconductor layer; and a gate layer having a generally vertical section on at least a portion of said vertical section of said third semiconductor layer over said first semiconductor layer, said gate layer having a generally horizontal section on said horizontal section of said third semiconductor layer.
Claim 6
Dependent Claim
180 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate; a first generally horizontal semiconductor layer on said substrate providing one of said source and drain; a generally horizontal insulator layer on said first semiconductor layer; a second generally horizontal semiconductor layer on said insulator layer and providing the other of said source and drain; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers; . a third semiconductor layer having a generally vertical section extending along said side of said mesa over said exposed edges of said first and second semiconductor layers and said insulator layer and providing a channel, said third semiconductor layer having a generally horizontal section on said substrate adjacent said first semiconductor layer; and a gate layer having a generally vertical section on at least a portion of said vertical section of said third semiconductor layer over said first semiconductor layer, said gate layer having a generally horizontal section on said horizontal section of said third semiconductor layer.
Claim 7
Dependent Claim
29 words
The invention according to claim 4 wherein said generally vertical section of said gate layer extends only over said first semiconductor layer and a portion of said insulator layer.
Claim 8
Dependent Claim
35 words
The invention according to claim 4 comprising a second generally horizontal insulator layer on said second semiconductor layer, and wherein said third semiconductor layer has a second generally horizontal section on said second insulator layer.
Claim 9
Dependent Claim
65 words
The invention according to claim 6 wherein said gate layer has a second generally horizontal section on said substrate, and said generally vertical section of said gate layer extends upwardly over said first insulator layer and said second semiconductor layer and said second insulator layer, and including a third generally horizontal gate layer section on said second generally horizontal section of said third semiconductor layer.
Claim 10
Dependent Claim
34 words
The invention according to claim 4 wherein said gate layer comprises a plurality of spaced gate fingers extending transversely across one or more of said edges and spaced therefrom by said third semiconductor layer.
Claim 11
Dependent Claim
32 words
The invention according to claim 8 wherein said gate fingers are joined at a generally horizontal contact pad section on said substrate adjacent said generally horizontal section of said third semiconductor layer.
Claim 12
Dependent Claim
40 words
The invention according to claim 8 comprising a second insulator layer having a generally vertical section on said vertical section of said third semiconductor layer and having a plurality of spaced finger-like recesses receiving said gate fingers in recessed relation.
Claim 13
Dependent Claim
113 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate having an upper surface; a first N++ layer epitaxially grown on said upper surface of said substrate; a first insulator layer epitaxially grown on said first N++ layer; a second N++ layer epitaxially grown on said first insulator layer: a second insulator layer epitaxially grcwn on said second N++ layer; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers; an N layer extending generally vertically along said side of said mesa over said exposed edges, said N layer covering at least said first N++ layer.
Claim 14
Dependent Claim
113 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate having an upper surface; a first N++ layer epitaxially grown on said upper surface of said substrate; a first insulator layer epitaxially grown on said first N++ layer; a second N++ layer epitaxially grown on said first insulator layer: a second insulator layer epitaxially grcwn on said second N++ layer; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers; an N layer extending generally vertically along said side of said mesa over said exposed edges, said N layer covering at least said first N++ layer.
Claim 15
Dependent Claim
64 words
The invention according to claim 11 wherein said second N++ layer extends horizontally beyond said second insulator layer to provide a generally horizontal upper surface contact area, and wherein said first N++ layer extends horizontally beyond said first insulator layer and said second N++ layer to provide a generally horizontal upper surface contact area, said contact areas providing respective source and drain electrode connections.
Claim 16
Dependent Claim
60 words
The invention according to claim 12 comprising: a first refractory metal layer covering said upper surface contact area of said first N++ layer; a first gold layer covering said first refractory metal layer; a second refractory metal layer covering said upper surface contact area of said second N++ layer; and a second gold layer covering said second refractory metal layer.
Claim 17
Dependent Claim
15 words
The invention according to claim 11 comprising a third insulator layer on said N layer.
Claim 18
Dependent Claim
47 words
The invention according to claim 14 wherein a portion of said third insulator layer is removed to expose said N layer, and comprising a refractory metal layer on said N layer where said third insulator layer is removed, and a gold layer covering said refractory metal layer.
Claim 19
Dependent Claim
24 words
The invention according to claim 15 wherein said refractory metal layer and said gold layer extend over each of said exposed edges perpendicularly thereto.
Claim 20
Dependent Claim
34 words
The invention according to claim 11 comprising a plurality of spaced gate fingers on said N layer extending transversely across at least one of said exposed edges and spaced therefrom by said N layer.
Claim 21
Dependent Claim
26 words
The invention according to claim 17 wherein said gate fingers are separated by a given distance to fully deplete said N layer surface at zero bias.
Claim 22
Dependent Claim
19 words
The invention according to claim 17 wherein the portions of said N layer between said gate fingers are removed.
Claim 23
Dependent Claim
25 words
The invention according to claim 17 wherein said gate fingers extend only across said first N++ layer and a portion of said first insulator layer.
Claim 24
Dependent Claim
122 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate; a first generally horizontal semiconductor layer on said substrate providing one of said source and drain: a generally horizontal insulator layer on said first semiconductor layer; a second generally horizontal semiconductor layer on said insulator layer and providing the other of said source and drain; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers, said first and second semiconductor layers extending from said side of said mesa in substantially laterally offset nonoverlapping paths; a third generally vertical semiconductor layer extending along said side of said mesa over said exposed edges and forming a channel.
Claim 25
Dependent Claim
122 words
A field effect transistor of the type having a source, a gate and a drain, comprising: a substrate; a first generally horizontal semiconductor layer on said substrate providing one of said source and drain: a generally horizontal insulator layer on said first semiconductor layer; a second generally horizontal semiconductor layer on said insulator layer and providing the other of said source and drain; said layers being stacked as a mesa structure having a generally vertical side exposing the edges of said layers, said first and second semiconductor layers extending from said side of said mesa in substantially laterally offset nonoverlapping paths; a third generally vertical semiconductor layer extending along said side of said mesa over said exposed edges and forming a channel.
Claim 26
Dependent Claim
87 words
The invention according to claim 21 wherein said first semiconductor layer extends horizontally beyond said first insulator layer and said second semiconductor layer, and comprising laterally offset first and second electrode layers on the upper surface of respective said first and second semiconductor layers, said first and second electrode layers being at different vertical heights spaced by the thickness of said insulator layer and said second semiconductor layer, said first and second semiconductor layers extending from respective said electrode layer areas in substantially laterally offset nonoverlapping paths.
Claim 27
Dependent Claim
31 words
The invention according to claim 22 wherein each of said first and second semiconductor layers includes an L-shaped section, the tip of one leg of the L being said exposed edge.
Claim 28
Dependent Claim
26 words
The invention according to claim 23 wherein said one leg of each L is the only area of overlap of said first and second semiconductor layers.
Claim 29
Dependent Claim
164 words
A processing method for fabricating an edge channel field effect transistor comprising the steps of: supplying a substrate with an upper surface; sequentially growing a first semiconductor layer, a first insulator layer, a second semiconductor layer and a second insulator layer; defining a mesa having sides exposing the edges of said layers; forming a third semiconductor layer over the top and sides of said mesa and the upper surface of said substrate; defining a channel in said third semicon- - ductor layer, and upper surface contact areas on said first and second semiconductor layers, by etching portions of said first and second insulator layers and said second and third semiconductor layers to leave said third semiconductor layer on a side of said mesa and to expose upper surface portions of said first and second semiconductor layers; and depositing source and drain electrode layers on said exposed portions of said first and second semiconductor layers, and a gate electrode layer on said third semiconductor layer.
Claim 30
Dependent Claim
164 words
A processing method for fabricating an edge channel field effect transistor comprising the steps of: supplying a substrate with an upper surface; sequentially growing a first semiconductor layer, a first insulator layer, a second semiconductor layer and a second insulator layer; defining a mesa having sides exposing the edges of said layers; forming a third semiconductor layer over the top and sides of said mesa and the upper surface of said substrate; defining a channel in said third semicon- - ductor layer, and upper surface contact areas on said first and second semiconductor layers, by etching portions of said first and second insulator layers and said second and third semiconductor layers to leave said third semiconductor layer on a side of said mesa and to expose upper surface portions of said first and second semiconductor layers; and depositing source and drain electrode layers on said exposed portions of said first and second semiconductor layers, and a gate electrode layer on said third semiconductor layer.
Claim 31
Dependent Claim
31 words
The invention according to claim 25 comprising selectively growing or implanting said first semiconductor layer in an L-shape, and performing carrier bombardment to define said second semiconductor layer in an L-shape.
Claim 32
Dependent Claim
25 words
The invention according to claim 26 comprising selectively defining said L-shapes to have areas of vertically spaced overlap only along one leg of the L.
References Cited (Backward Citations)
No citation records indexed.
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