Process for forming twin well CMOS integrated circuits

Claim 1

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductively type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (j) selectivity forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; (l) forming interconnect contacts to the exposed portions of said thin metal layer by: forming thick metal plugs in apertures in said insulator layer formed in step (k), said thick metal plugs containing the metal of said thin metal layer; forming a thin adhesion metal layers over said insulator layer and said thick metal plugs; and forming an interconnect metal layer over said transition metal layer.

Claim 2

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductively type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (j) selectivity forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; (l) forming interconnect contacts to the exposed portions of said thin metal layer by: forming thick metal plugs in apertures in said insulator layer formed in step (k), said thick metal plugs containing the metal of said thin metal layer; forming a thin adhesion metal layers over said insulator layer and said thick metal plugs; and forming an interconnect metal layer over said transition metal layer.

Claim 3

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (j) selectively forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (l) forming interconnect contacts to the exposed portions of said thin metal layer by forming a multilevel interconnect metal layer-insulator structure to selected ones of the exposed portions of said thin metal layer.

Claim 4

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (j) selectively forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (l) forming interconnect contacts to the exposed portions of said thin metal layer by forming a multilevel interconnect metal layer-insulator structure to selected ones of the exposed portions of said thin metal layer.

Claim 9

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and wherein said field insulator layer is effectively hardened against radiation such that said field insulator layer exhibits a flat-band voltage shift thereacross no greater than 20 volts over a total radition dose range of at least 10 5 rads; said field insulator layer comprises a laminated structure of a thermally grown insulator layer and a deposited insulator layer thereon; said body of semiconductor material comprises a silicon body and said laminated structure comprises a first layer of silicon dioxide thermally grown on said effectively planar surface of said silicon body and a second layer of chemically vapor deposited phosphosilicate glass atop said first layer of silicon dioxide; step (d) includes forming a layer of material of which said first and second gates are made on said radiation hardened field insulator layer; and further comprising the steps of: (j) selectively forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (l) forming interconnect contacts to the exposed portions of said thin metal layer; and wherein step (j) includes forming said thin metal layer on the layer of material formed in step (d); and wherein step (l) includes the steps of forming thick metal plugs in apertures in said insulator layer formed in step (k), said thick metal plugs containing the metal of said thin metal layer; forming a thin adhesion metal layer over said insulator layer and said thick metal plugs; and forming an interconnect metal layer over said adhesion metal layer.

Claim 10

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and wherein said field insulator layer is effectively hardened against radiation such that said field insulator layer exhibits a flat-band voltage shift thereacross no greater than 20 volts over a total radition dose range of at least 10 5 rads; said field insulator layer comprises a laminated structure of a thermally grown insulator layer and a deposited insulator layer thereon; said body of semiconductor material comprises a silicon body and said laminated structure comprises a first layer of silicon dioxide thermally grown on said effectively planar surface of said silicon body and a second layer of chemically vapor deposited phosphosilicate glass atop said first layer of silicon dioxide; step (d) includes forming a layer of material of which said first and second gates are made on said radiation hardened field insulator layer; and further comprising the steps of: (j) selectively forming a thin metal layer on said source and drain regions and on said first and second gates; (k) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (l) forming interconnect contacts to the exposed portions of said thin metal layer; and wherein step (j) includes forming said thin metal layer on the layer of material formed in step (d); and wherein step (l) includes the steps of forming thick metal plugs in apertures in said insulator layer formed in step (k), said thick metal plugs containing the metal of said thin metal layer; forming a thin adhesion metal layer over said insulator layer and said thick metal plugs; and forming an interconnect metal layer over said adhesion metal layer.

Claim 15

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and wherein said field insulator layer is effectively hardened against radiation such that said field insulator layer exhibits a flat-band voltage shift thereacross no greater than 20 volts over a total radiation dose range of at least 10 5 rads; said field insulator layer comprises a laminated structure of a thermally grown insulator layer and a deposited insulator layer thereon; said body of semiconductor material comprises a silicon body and said laminated structure comprises a first layer of silicon dioxide thermally grown on said effectively planar surface of said silicon body and a second layer of chemically vapor deposited phosphosilicate glass atop said first layer of silicon dioxide; step (d) includes forming a layer of material of which said first and second gates are made on said radiation hardened field insulator layer; and wherein step (g) includes forming insulator spacers extending laterally from said layer of material onto said radiation hardened field insulator layer.

Claim 16

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and wherein said field insulator layer is effectively hardened against radiation such that said field insulator layer exhibits a flat-band voltage shift thereacross no greater than 20 volts over a total radiation dose range of at least 10 5 rads; said field insulator layer comprises a laminated structure of a thermally grown insulator layer and a deposited insulator layer thereon; said body of semiconductor material comprises a silicon body and said laminated structure comprises a first layer of silicon dioxide thermally grown on said effectively planar surface of said silicon body and a second layer of chemically vapor deposited phosphosilicate glass atop said first layer of silicon dioxide; step (d) includes forming a layer of material of which said first and second gates are made on said radiation hardened field insulator layer; and wherein step (g) includes forming insulator spacers extending laterally from said layer of material onto said radiation hardened field insulator layer.

Claim 17

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and (j) subjecting the source and drain regions formed in steps (h) and (i) to a rapid thermal anneal treatment.

Claim 18

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) providing a semiconductor body having in a planar surface thereof a first region of a first conductivity type and a second region of a second conductivity type; (b) selectively forming a field insulator layer on said planar surface so as to expose a surface portion of said first region and a surface portion of said second region; (c) forming first and second gate insulator layers on said surface portion of said first region and on said surface portion of said second region, respectively; (d) forming first and second gates on said first and second gate insulator layers, respectively; (e) introducing impurities of said second conductivity type into said first region using said first gate as a mask to form shallow source and drain regions therein; (f) introducing impurities of said first conductivity type into said second region using said second gate as a mask to form shallow source and drain regions therein; (g) forming insulative spacers extending laterally from said first and second gates and from said field insulator layer over said source and drain regions; (h) introducing impurities of said second conductivity type into said first gate, and into said first region using said first gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; (i) introducing impurities of said first conductivity type into said second gate, and into said second region using said second gate and spacers as a mask to form deep source and drain regions therein having a depth and an impurity concentration greater than said shallow source and drain regions therein; and (j) subjecting the source and drain regions formed in steps (h) and (i) to a rapid thermal anneal treatment.

Claim 19

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respective first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; (g) forming a thin metal layer on said source and drain regions and on said first and second gates; (h) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (i) forming interconnect contacts to the exposed portions of said thin metal layer by forming a multilevel interconnect metal layer insulator structure to selected ones of exposed portions of said thin metal layer.

Claim 20

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respective first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; (g) forming a thin metal layer on said source and drain regions and on said first and second gates; (h) selectively forming an insulator layer over said surface to expose portions of said thin metal layer; and (i) forming interconnect contacts to the exposed portions of said thin metal layer by forming a multilevel interconnect metal layer insulator structure to selected ones of exposed portions of said thin metal layer.

Claim 21

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respectively first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; and (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; and wherein step (c) includes forming a layer of material of which said first and second gates are made on said first relatively thick field insulator portion of said insulator layer.

Claim 22

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respectively first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; and (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; and wherein step (c) includes forming a layer of material of which said first and second gates are made on said first relatively thick field insulator portion of said insulator layer.

Claim 31

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respective first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; and (g) subjecting the source and drain regions formed in steps (e) and (f) to a rapid thermal anneal treatment.

Claim 32

A method of forming complementary insulated gate field effect transistors comprising the steps of: (a) forming, in a planar surface of semiconductor material, a first well region of a first conductivity type and a second well region of a second conductivity type each of said well regions having retrograde impurity distribution profiles therein; (b) selectively forming an insulator layer comprising a first relatively thick field insulator portion prescribing respective first and second surface areas of said first and second well regions, and first and second relatively thin gate insulator portions within said surface areas, respectively; (c) forming respective first and second gates on said first and second relatively thin portions of said insulator layer; (d) forming insulative spacers extending laterally from said first and second gates and from said relatively thick field insulator portions of said insulator layer over said first and second surface areas; (e) introducing impurities of said second conductivity type into said first surface area of said first well region, using said first gate and spacers as a mask to form source and drain regions; (f) introducing impurities of said first conductivity type into said second surface area of said second well region, using said second gate and spacers as a mask to form source and drain regions therein; and (g) subjecting the source and drain regions formed in steps (e) and (f) to a rapid thermal anneal treatment.