US4490736A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of making
Assignee: Texas Instruments Inc
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Filing: 1980-05-19
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Granted: 1984-12-25
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Expires: 2000-05-19
Abstract
Abstract Semiconductor devices are made by a process in which impurity is introduced, by ion implant, for example, after electrode layers are in place so that inaccuracies in alignment of masks or patterns are compensated. The implanted impurity changes the electrical characteristics of portions of the semiconductor device affected by the registration inaccuracies whereby malfunctions in the completed devices are prevented.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:40
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
144 words
An integrated circuit device having insulated gate field effect transistors comprising: (a) a silicon substrate, (b) a tank region formed in a face of said substrate, (c) a first surface area of said face spaced from the tank region for inclusion of a first transistor, (d) a second surface area of said face within the tank region for inclusion of a second transistor, (e) first and second conductive gates overlying thin gate insulator on said first and second surface areas, respectively, (f) source and drain regions in said face at the first surface area on opposite sides of the first gate, (g) source and drain regions in said face at the second surface area on opposite sides of the second gate, (h) and self aligned implanted regions in said first and second surface areas, respectively, adjacent the gates and said source and drain regions.
Claim 2
Dependent Claim
144 words
An integrated circuit device having insulated gate field effect transistors comprising: (a) a silicon substrate, (b) a tank region formed in a face of said substrate, (c) a first surface area of said face spaced from the tank region for inclusion of a first transistor, (d) a second surface area of said face within the tank region for inclusion of a second transistor, (e) first and second conductive gates overlying thin gate insulator on said first and second surface areas, respectively, (f) source and drain regions in said face at the first surface area on opposite sides of the first gate, (g) source and drain regions in said face at the second surface area on opposite sides of the second gate, (h) and self aligned implanted regions in said first and second surface areas, respectively, adjacent the gates and said source and drain regions.
Claim 3
Dependent Claim
15 words
A device according to claim 1 wherein the first and second gates are polycrystalline silicon.
Claim 4
Dependent Claim
19 words
A device according to claim 1 wherein the source and drain regions are much deeper than said implanted regions.
Claim 5
Dependent Claim
28 words
A device according to claim 1 wherein the implanted regions include both P and N type and extend along the sides of the gates from source to drain.
Claim 6
Dependent Claim
146 words
An integrated circuit device having insulated gate field effect transistors comprising: (a) a silicon substrate, (b) a first region formed in a face of said substrate, (c) a first surface area of said face spaced from the first region for inclusion of a first transistor, (d) a second surface area of said face within the first region for inclusion of the second transistor, (e) first and second gates overlying thin gate insulator on said first and second surface areas, (f) source and drain regions in said face at the first surface area on opposite sides of the first gate, (g) source and drain regions in said face at the second surface area on opposite sides of the second gate, (h) and self-aligned implanted regions of both impurity types in said first and second surface areas, adjacent the gates and extending between said source and drain regions.
Claim 7
Dependent Claim
146 words
An integrated circuit device having insulated gate field effect transistors comprising: (a) a silicon substrate, (b) a first region formed in a face of said substrate, (c) a first surface area of said face spaced from the first region for inclusion of a first transistor, (d) a second surface area of said face within the first region for inclusion of the second transistor, (e) first and second gates overlying thin gate insulator on said first and second surface areas, (f) source and drain regions in said face at the first surface area on opposite sides of the first gate, (g) source and drain regions in said face at the second surface area on opposite sides of the second gate, (h) and self-aligned implanted regions of both impurity types in said first and second surface areas, adjacent the gates and extending between said source and drain regions.
Claim 8
Dependent Claim
15 words
A device according to claim 5 wherein the first and second gates are polycrystalline silicon.
Claim 9
Dependent Claim
26 words
A device according to claim 6 wherein said first region in said face is N-type, said first transistor is N-channel, and said second transistor is P-channel.
Claim 10
Dependent Claim
19 words
A device according to claim 5 wherein the source and drain regions are much deeper than said implanted regions.
Claim 11
Independent Claim
134 words
A method for manufacturing a semiconductor device comprising the steps of forming an isolating region including a field oxide film on one major surface of semiconductor substrate of one conductivity type, forming a gate insulator film on said one major surface of said semiconductor substrate at a position surrounded by said isolating region, depositing on said gate insulator film a conductive film to provide a gate electrode, shaping the width edges of said gate electrode, and thereafter introducing impurities of said one conductivity type into said semiconductor substrate between the width edges of said gate electrode and said field oxide film opposed thereto to form a channel stopper region so thata boundary line of said channel stopper region is substantially in coincidence with said width edge of said gate electrode in the plane view.
Claim 12
Independent Claim
134 words
A method for manufacturing a semiconductor device comprising the steps of forming an isolating region including a field oxide film on one major surface of semiconductor substrate of one conductivity type, forming a gate insulator film on said one major surface of said semiconductor substrate at a position surrounded by said isolating region, depositing on said gate insulator film a conductive film to provide a gate electrode, shaping the width edges of said gate electrode, and thereafter introducing impurities of said one conductivity type into said semiconductor substrate between the width edges of said gate electrode and said field oxide film opposed thereto to form a channel stopper region so thata boundary line of said channel stopper region is substantially in coincidence with said width edge of said gate electrode in the plane view.
Claim 13
Dependent Claim
40 words
A method for manufacturing a semiconductor device of claim 9, in which said impurities of said one conductivity type are introduced by ion implantation through said gate insulator film entending from under said gate electrode to said field oxide film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |