Data latch circuit having non-volatile memory cell equipped with common floating gate and stress relaxing transistor

Claim 2

A data latch circuit comprising: a non-volatile memory cell having a writing transistor and a reading transistor, and disposed to store data, the writing transistor and the reading transistor having a control gate and a floating gate, the non-volatile memory cell being an erasable/programmable read only memory cell, the writing transistor and the reading transistor having the floating gate in common, the writing transistor being of an enhancement type the reading transistor being made as a depletion type in an initial state assumed before dam is written therein, the control gate of the reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent of a power supply voltage; and protection means for protecting the non-volatile memory cell by relaxing stress applied thereto, the protection means including a depletion type stress-relaxing transistor which has a gate grounded and a current path having a first end connected to a first end of a current path of the reading transistor such that a potential of the first end of the reading transistor is clamped.

Claim 3

The data latch circuit according to claim 1, further comprising an external terminal and output means for outputting from the external terminal potentials corresponding to on and off states of the non-volatile memory cell.

Claim 4

The data latch circuit according to claim 2, wherein the output means includes a MOS transistor having a current path which has a first end connected to a second end of the current path of the reading transistor, first load means connected between the external terminal and a second end of the current path of the MOS transistor, and second load means connected between said power supply voltage and the second end of the current path of the MOS transistor.

Claim 5

The data latch circuit according to claim 2, wherein a second end of the current path of the stress relaxing transistor is connected to said power supply voltage.

Claim 6

The data latch circuit according to claim 2, further comprising a write control transistor which has a current path connected between a drain of the writing transistor and a power supply voltage used for writing, and has a gate to be supplied with said power supply voltage for writing at a writing time and to be supplied with a ground potential at a time other than the writing time.

Claim 7

The data latch circuit according to claim 1, wherein the reading transistor is made as a depletion type as a result of ion implantation.

Claim 8

The data latch circuit according to claim 1, wherein the reading transistor is made as a depletion type as a result of erasure for initialization.

Claim 9

The data latch circuit according to claim 1, wherein the constant voltage, independent of the power supply voltage applied to the control gate of the reading transistor during normal operation, is a ground potential.

Claim 10

The data latch circuit according to claim 1, wherein the writing transistor and the reading transistor have a common control gate.

Claim 11

The data latch circuit according to claim 1, wherein the reading transistor and the writing transistor have their respective control gates, and the control gate of the reading transistor is connected to a ground terminal.

Claim 12

The data latch circuit according to claim 1, further including other transistors wherein a gate length of the writing transistor is shorter than gate lengths of the other transistors, and a gate length of the reading transistor is longer than the gate lengths of the other transistors.

Claim 13

A data latch circuit comprising: a non-volatile memory cell having a writing transistor and a reading transistor, and disposed to store data, the writing transistor and the reading transistor having a control gate and a floating gate, the non-volatile memory cell being an erasable/programmable read only memory, the writing transistor and the reading transistor having the floating gate in common, the writing transistor being of an enhancement type, the reading transistor being made as a depletion type in an initial state assumed before data is written therein, the control gate of the reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent of a power supply voltage; latch means for latching potentials corresponding to on and off states of the nonvolatile memory cell; and protection means for protecting the non-volatile memory cell by relaxing stress applied thereto, the protection means including a depletion type stress-relaxing transistor which has a gate grounded a current path having a first; end connected to a first end of a current path of the reading transistor and a second end connected to the latch means, such that a potential of the first end of the reading transistor is clamped.

Claim 14

A data latch circuit comprising: a non-volatile memory cell having a writing transistor and a reading transistor, and disposed to store data, the writing transistor and the reading transistor having a control gate and a floating gate, the non-volatile memory cell being an erasable/programmable read only memory, the writing transistor and the reading transistor having the floating gate in common, the writing transistor being of an enhancement type, the reading transistor being made as a depletion type in an initial state assumed before data is written therein, the control gate of the reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent of a power supply voltage; latch means for latching potentials corresponding to on and off states of the nonvolatile memory cell; and protection means for protecting the non-volatile memory cell by relaxing stress applied thereto, the protection means including a depletion type stress-relaxing transistor which has a gate grounded a current path having a first; end connected to a first end of a current path of the reading transistor and a second end connected to the latch means, such that a potential of the first end of the reading transistor is clamped.

Claim 15

The data latch circuit according to claim 12, further comprising selector means responsive to an output of the latch means for selecting one of an address signal and an inverted signal of the address signal.

Claim 16

The data latch circuit according to claim 12, wherein the reading transistor is made as a depletion type as a result of ion implantation.

Claim 17

The data latch circuit according to claim 12, wherein the reading transistor is made as a depletion type as a result of erasure for initialization.

Claim 18

The data latch circuit according to claim 12, wherein the constant voltage, independent of the power supply voltage applied to the control gate of the reading transistor during normal operation, is a ground potential.

Claim 19

The data latch circuit according to claim 12, wherein the writing transistor and the reading transistor have a common control gate.

Claim 20

The data latch circuit according to claim 12, wherein the reading transistor and the writing transistor have their respective control gates, and the control gate of the reading transistor is connected to a ground terminal.

Claim 21

The data latch circuit according to claim 12, further comprising a write control transistor which has a current path connected between a drain of the writing transistor and a power supply voltage used for writing, and has a gate to be supplied with said power supply voltage for writing at a writing time and to be supplied with a ground potential at a time other than the writing time.

Claim 22

The data latch circuit according to claim 12, wherein the latch means includes a CMOS inverter circuit, and a p-channel MOS transistor for performing feedback control, which has a source connected to said power supply voltage, a drain connected to an input node of the CMOS inverter circuit, and a gate connected to an output node of the CMOS inverter circuit.

Claim 23

The data latch circuit according to claim 20, further comprising a capacitor connected between the input node or the CMOS inverter circuit and said power supply voltage.

Claim 24

The data latch circuit according to claim 12, further comprising other transistors, wherein the gate length of the writing transistor is shorter than gate lengths of the other transistors, and the gate length of the reading transistor is longer than the gate length of the other transistors.