High-speed memory with a limiter of the drain voltage of the cells

Claim 2

An erasable and electrically programmable memory, comprising: an array of rows and columns, each column having a plurality of memory cells and a respective bit line, and each said bit line having a respective preload circuit; a respective compensation circuit connected in series between each of said memory cells and the respective bit line of said corresponding column, each said compensation circuit including a compensation transistor and an inverter, wherein an output of said inverter is connected to a gate of said compensation transistor; and a voltage limiter connected to said gate of said compensation transistor to prevent the value of the voltage at said gate of said compensation transistor from rising above a limit voltage imposed by said voltage limiter.

Claim 3

A memory in accordance with claim 1 wherein said voltage limiter comprises at least one current limiting transistor mounted as a diode, imposing a limit voltage equal to the threshold voltage of said at least one current limiting transistor.

Claim 4

A memory in accordance with claim 1 wherein said voltage limiter comprises at least two current limiting transistors connected in series, each current limiting transistor being mounted as a diode, such that said voltage limiter imposes a limit voltage equal to the sum of the threshold voltages of said at least two current limiting transistors.

Claim 5

A memory in accordance with claim 1 wherein said voltage limiter comprises first and second current limiting transistors connected in series between the gate of the compensation transistor and a reference voltage, with a drain of the first current limiting transistor being connected to the gate of the compensation transistor, a drain of the second current limiting transistor being connected to a source of the first current limiting transistor, a source of the second current limiting transistor being connected to said reference voltage, a gate of the first current limiting transistor being connected to the drain of the first current limiting transistor, and a gate of the second current limiting transistor being connected to the drain of the second current limiting transistor.

Claim 6

A memory in accordance with claim 1 wherein each memory cell is a floating gate transistor having a floating gate, a control gate connected to an associated word line, a drain connected to the associated bit line, and a source connected to a reference potential.

Claim 7

A memory in accordance with claim 1 wherein each compensation transistor is more resistive than each memory cell, a drain of each compensation transistor is connected to the respective bit line, a source of each compensation transistor is connected to each of the memory cells in the column associated with the respective bit line, and the source of each compensation transistor is also connected to an input of the respective inverter.

Claim 8

A memory in accordance with claim 6 wherein said voltage limiter comprises at least one current limiting transistor connected as a diode, imposing a limit voltage equal to the threshold voltage of said at least one current limiting transistor.

Claim 9

A memory in accordance with claim 6 wherein said voltage limiter comprises at least two current limiting transistors connected in series, each current limiting transistor being connected as a diode, such that said voltage limiter imposes a limit voltage equal to the sum of the threshold voltages of said at least two current limiting transistors.

Claim 10

A memory in accordance with claim 6 wherein said voltage limiter comprises first and second current limiting transistors connected in series between the gate of the compensation transistor and a reference voltage, with the drain of the first current limiting transistor being connected to the gate of a compensation transistor, a drain of the second current limiting transistor being connected to a source of the first current limiting transistor, a source of the second current limiting transistor being connected to said reference voltage, a gate of the first current limiting transistor being connected to the drain of the first current limiting transistor, and a gate of the second current limiting transistor being connected to the drain of the second current limiting transistor.

Claim 11

A memory in accordance with claim 9 wherein a reading amplifier is connected to the bit line to read the selected memory cell.

Claim 12

A memory in accordance with claim 10 wherein each memory cell is a floating gate transistor having a floating gate, a control gate connected to an associated word line, a drain connected to the associated bit line, and a source connected to a reference potential.

Claim 13

A memory in accordance with claim 1 wherein a reading amplifier is connected to the bit line to read the selected memory cell.

Claim 14

A memory in accordance with claim 1 wherein the pre-load circuit comprises a pre-load transistor connected between a supply voltage and the bit line, with a gate of the pre-load transistor being connectable to a reference voltage when the associated bit line is selected.

Claim 15

A memory in accordance with claim 13 wherein said compensation transistor is more resistive than each memory cell and said pre-load transistor is more resistive than said compensation transistor.

Claim 16

A memory in accordance with claim 1 wherein the pre-load circuit comprises a pre-load transistor connected between a supply voltage and the bit line, with a gate of the pre-load transistor being connectable to a reference voltage when the associated bit line is selected; wherein the pre-load transistor, the compensation transistor, and each memory cell associated with a bit line are connected in series between the supply voltage and the reference voltage.

Claim 17

A memory in accordance with claim 1 wherein the pre-load circuit comprises a pre-load transistor, with a drain of the pre-load transistor being connected to a supply voltage, a source of the pre-load transistor being connected to the associated bit line, and a gate of the pre-load transistor being connectable to a memory ground when the associated bit line is selected; wherein the pre-load transistor, the compensation transistor, and each memory cell associated with a bit line are connected in series between the supply voltage and the memory ground, with a drain of the compensation transistor being connected to the respective bit line, a source of the compensation transistor being connected to a first terminal of each of the memory cells in the column associated with the respective bit line, the source of the compensation transistor being also connected to an input of the respective inverter, and another other terminal of each of the memory cells in the column associated with the respective bit line being connected to the memory ground.

Claim 18

A memory in accordance with claim 16 wherein a reading amplifier is connected to the bit line to read the selected memory cell.

Claim 19

A memory in accordance with claim 17 wherein said voltage limiter comprises at least one current limiting transistor connected as a diode, imposing a limit voltage equal to the threshold voltage of said at least one current limiting transistor.

Claim 20

A memory in accordance with claim 17 wherein said voltage limiter comprises at least two current limiting transistors connected in series, each current limiting transistor being connected as a diode, such that said voltage limiter imposes a limit voltage equal to the sum of the threshold voltages of said at least two current limiting transistors.

Claim 21

A memory in accordance with claim 17 wherein said voltage limiter comprises first and second current limiting transistors connected in series between the gate of the compensation transistor and a reference voltage, with a drain of the first current limiting transistor being connected to the gate of a compensation transistor, the drain of the second current limiting transistor being connected to a source of the first current limiting transistor, a source of the second current limiting transistor being connected to said reference voltage, a gate of the first current limiting transistor being connected to the drain of the first current limiting transistor, and a gate of the second current limiting transistor being connected to the drain of the second current limiting transistor.

Claim 22

A memory in accordance with claim 20 wherein each compensation transistor is more resistive than each memory cell and each pre-load transistor is more resistive than each compensation transistor.

Claim 23

A memory in accordance with claim 21 wherein each memory cell is a floating gate transistor having a floating gate, a control gate connected to an associated word line, a drain connected to the associated bit line, and a source connected to a reference potential.

Claim 24

A high-speed nonvolatile memory integrated circuit, comprising: an array, arrange in rows and columns, of N-channel floating-gate memory cells; multiple conductive wordlines and bitlines within said array, said wordlines running parallel to said rows and said bitlines running parallel to said columns; and pre-load and read circuitry operatively connected to each of said bitlines; said memory cells each having a source connected to ground, and a gate connected to a respective one of said wordlines; each said memory cell being operatively connected to a respective compensation circuit comprising a respective N-channel compensation transistor, an inverter connected from drain to gate of said compensation transistor, and a voltage limiter circuit connected to said gate of said compensation transistor.

Claim 25

A high-speed nonvolatile memory integrated circuit, comprising: an array, arrange in rows and columns, of N-channel floating-gate memory cells; multiple conductive wordlines and bitlines within said array, said wordlines running parallel to said rows and said bitlines running parallel to said columns; and pre-load and read circuitry operatively connected to each of said bitlines; said memory cells each having a source connected to ground, and a gate connected to a respective one of said wordlines; each said memory cell being operatively connected to a respective compensation circuit comprising a respective N-channel compensation transistor, an inverter connected from drain to gate of said compensation transistor, and a voltage limiter circuit connected to said gate of said compensation transistor.

Claim 26

The integrated circuit of claim 23, wherein said voltage limiter circuit comprises a plurality of diode-connected transistors.

Claim 27

The integrated circuit of claim 23, wherein said voltage limiter circuit comprises exactly two diode-connected N-channel transistors.

Claim 28

The integrated circuit of claim 23, wherein said compensation transistor is more resistive than a respective transistor of each said memory cell.

Claim 29

A high-speed nonvolatile memory integrated circuit, comprising: an array, arranged in rows and columns, of N-channel floating-gate memory cells; multiple conductive wordlines and bitlines within said array, said wordlines running parallel to said rows and said bitlines running parallel to said columns; and read circuitry, and a P-channel load transistor, operatively connected to each of said bitlines; said memory cells each having a source connected to ground, and a gate connected to a respective one of said wordlines; each said cell being operatively connected to a respective compensation circuit comprising a respective N-channel compensation transistor, which is more resistive than a respective transistor of each said memory cell an inverter connected from drain to gate of said compensation transistor, and a voltage limiter circuit connected to said gate of said compensation transistor, and configured to limit the maximum voltage at said gate of said compensation transistor.

Claim 30

A high-speed nonvolatile memory integrated circuit, comprising: an array, arranged in rows and columns, of N-channel floating-gate memory cells; multiple conductive wordlines and bitlines within said array, said wordlines running parallel to said rows and said bitlines running parallel to said columns; and read circuitry, and a P-channel load transistor, operatively connected to each of said bitlines; said memory cells each having a source connected to ground, and a gate connected to a respective one of said wordlines; each said cell being operatively connected to a respective compensation circuit comprising a respective N-channel compensation transistor, which is more resistive than a respective transistor of each said memory cell an inverter connected from drain to gate of said compensation transistor, and a voltage limiter circuit connected to said gate of said compensation transistor, and configured to limit the maximum voltage at said gate of said compensation transistor.

Claim 31

The integrated circuit of claim 27, wherein said voltage limiter circuit comprises a plurality of diode-connected transistors.

Claim 32

The integrated circuit of claim 27, wherein said voltage limiter circuit comprises exactly two diode-connected N-channel transistors.

Claim 33

The integrated circuit of claim 27, wherein said load transistor is more resistive than each said compensation transistor.