US5231602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for improving the endurance of floating gate devices
Assignee: Lattice Semiconductor Corp
•
Filing: 1990-04-25
•
Granted: 1993-07-27
•
Expires: 2010-04-25
Abstract
Abstract An apparatus and method for improving the reliability of floating gate transistors used in memory cell applications by controlling the electric field induced across the tunnel oxide region of the floating gate transistor when discharging electrons from floating gate is provided. The invention comprises method and apparatus for varying the resistance applied to the drain electrode of the floating gate device and/or varying the voltage applied to the source electrode of the floating gate device to control the electric field in the tunnel oxide region of the floating gate device. In the preferred embodiment of the invention utilized in an EEPROM memory cell, both a method and an apparatus applying a variable resistance and a method and an apparatus applying a variable voltage are utilized simultaneously. The method and apparatus provide an optimal electric field intensity to control electron tunneling in the tunnel region of the floating gate device during discharge of electrons from the floating gate.
Inventors
- 👤 Nader A. Radjy
- 👤 Michael S. Briner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
94 words
1. A self-limited programming circuit, comprising: a first MOS transistor having a floating gate, oxide layer, source electrode, and drain electrode; and means for regulating the electric field potential across said oxide layer, comprising a variable resistor coupled to said drain electrode and means for controlling the voltage applied to said source electrode of said first MOS transistor, wherein said means for controlling and said variable resistor are set to optimize the electric field potential across the oxide layer during discharge of electrons from said floating gate to minimize current through the oxide layer.
Claim 2
Dependent Claim
94 words
1. A self-limited programming circuit, comprising: a first MOS transistor having a floating gate, oxide layer, source electrode, and drain electrode; and means for regulating the electric field potential across said oxide layer, comprising a variable resistor coupled to said drain electrode and means for controlling the voltage applied to said source electrode of said first MOS transistor, wherein said means for controlling and said variable resistor are set to optimize the electric field potential across the oxide layer during discharge of electrons from said floating gate to minimize current through the oxide layer.
Claim 3
Dependent Claim
25 words
The self limited programming circuit of claim 1 wherein said means for controlling the voltage applied to said source electrode comprises a variable voltage source.
Claim 4
Dependent Claim
119 words
In a semiconductor memory array: (a) a plurality of memory cells each of said memory cells comprising a MOS transistor having a floating gate, oxide layer, source electrode and drain electrode, and (b) at least one self-limited programming circuit for reducing the failure rate of said plurality of memory cells in said array, said self-limited programming circuit including means for controlling the voltage applied to said source electrode of at least one of said MOS transistors to regulate an electric field potential across said oxide layer during the discharge of electrons from said floating gate to minimize the quantity of current through the oxide layer of said first MOS transistor during the discharge of electrons from the floating gate.
Claim 5
Dependent Claim
119 words
In a semiconductor memory array: (a) a plurality of memory cells each of said memory cells comprising a MOS transistor having a floating gate, oxide layer, source electrode and drain electrode, and (b) at least one self-limited programming circuit for reducing the failure rate of said plurality of memory cells in said array, said self-limited programming circuit including means for controlling the voltage applied to said source electrode of at least one of said MOS transistors to regulate an electric field potential across said oxide layer during the discharge of electrons from said floating gate to minimize the quantity of current through the oxide layer of said first MOS transistor during the discharge of electrons from the floating gate.
Claim 6
Dependent Claim
29 words
The self-limited programming circuit as claimed in claim 3, further including resistance means for controlling the current applied to said drain electrode of said at least one MOS transistor.
Claim 7
Dependent Claim
31 words
The self-limited programming circuit as claimed in claim 3 wherein said means for controlling comprises a variable voltage source coupled to said source electrode of said at least one MOS transistor.
Claim 8
Dependent Claim
123 words
An electrically erasable programmable read only memory (E 2 PROM) cell, said E 2 PROM cell having a select transistor including source electrode and drain electrode, and a MOS transistor including a floating gate, oxide layer, source electrode, and drain electrode, comprising: variable resistance means coupled to said drain electrode of said select transistor for selectively regulating current through said oxide layer of said MOS transistor; and variable voltage source means coupled to said source electrode of said MOS transistor for selectively regulating the voltage applied to said source electrode of said MOS transistor; wherein said variable resistance means and variable voltage source means operate to minimize the electric field potential across said oxide layer during discharge of electrons from said floating gate.
Claim 9
Dependent Claim
123 words
An electrically erasable programmable read only memory (E 2 PROM) cell, said E 2 PROM cell having a select transistor including source electrode and drain electrode, and a MOS transistor including a floating gate, oxide layer, source electrode, and drain electrode, comprising: variable resistance means coupled to said drain electrode of said select transistor for selectively regulating current through said oxide layer of said MOS transistor; and variable voltage source means coupled to said source electrode of said MOS transistor for selectively regulating the voltage applied to said source electrode of said MOS transistor; wherein said variable resistance means and variable voltage source means operate to minimize the electric field potential across said oxide layer during discharge of electrons from said floating gate.
Claim 10
Independent Claim
138 words
A method for improving the endurance of a memory array having a plurality of floating gate MOS transistors, each MOS transistor having a gate electrode, a floating gate, source and drain electrodes, and an oxide layer separating said source and drain electrodes from said floating gate, said MOS transistors for storing data in the form of electrons on the floating gates thereof, the method comprising: (a) discharging electrons from the floating gates by applying a first voltage to the drain electrodes of the plurality of floating gate MOS transistors and a second voltage to the gate electrodes of the floating gate MOS transistors; and (b) simultaneously controlling an electric field potential of each such MOS transistor during the discharge thereof by controlling a quantity of a variable resistance in series with the drain electrode of each MOS transistor.
Claim 11
Independent Claim
138 words
A method for improving the endurance of a memory array having a plurality of floating gate MOS transistors, each MOS transistor having a gate electrode, a floating gate, source and drain electrodes, and an oxide layer separating said source and drain electrodes from said floating gate, said MOS transistors for storing data in the form of electrons on the floating gates thereof, the method comprising: (a) discharging electrons from the floating gates by applying a first voltage to the drain electrodes of the plurality of floating gate MOS transistors and a second voltage to the gate electrodes of the floating gate MOS transistors; and (b) simultaneously controlling an electric field potential of each such MOS transistor during the discharge thereof by controlling a quantity of a variable resistance in series with the drain electrode of each MOS transistor.
Claim 12
Dependent Claim
36 words
The method for improving the endurance of a memory array as claimed in the claim 7 wherein said step (b) is performed by controlling a variable voltage applied to the source of each said MOS transistor.
Claim 13
Dependent Claim
48 words
The method for improving the endurance of a memory array as claimed in claim 7 wherein said step (b) is performed by simultaneously applying a variable resistance to the drain electrode of each MOS transistor; and controlling a variable voltage applied to the source of each MOS transistor.
References Cited (Backward Citations)
US4627027A
Cited
US4780750A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-26 | 1997-01-25 | 1997-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-26 | 2001-01-25 | 2001-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-26 | 2005-01-25 | 2005-07-27 | $7700.00 | Window Closed / Lapsed |