US4823320A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable fuse circuit for an integrated-circuit chip
Assignee: Texas Instruments Inc
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Filing: 1986-05-08
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Granted: 1989-04-18
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Expires: 2006-05-08
Abstract
Abstract A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.
Inventors
- 👤 Michael C. Smayling
- 👤 Sebastiano D'Arrigo
- 👤 Giuliano Imondi
- 👤 Sossio Vergara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/04; G11C16/0408; G11C16/0441; G11C16/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
221 words
A fuse circuit for an integrated circuit device, comprising: a non-volatile programmable memory element having two programmed states; a programming circuit coupled to said memory element for programming said memory element in response to a programming control signal; a read circuit coupled to said memory element for detecting the programmed state of said programming circuit and for generating a low voltage level for one of said two programmed states and a high voltage level for the other of said programmed states; and a pass transistor coupled to said read circuit switchable from an open to a closed condition in response to a change in output voltage level of said read circuit; wherein a NOR gate is used for forcing the output of said read circuit to zero in response to a SPOR input signal to said NOR gate; wherein said integrated circuit device includes a read line coupled to said read circuit through a read pass gate transistor which is turned off during a write or programming mode or in response to a SPOR signal being high; and wherein said read circuit includes a transistor coupled between supply voltage V DD and a read end of a source to a drain path of said read pass gate transistor and responsive to conduct on the opening of said read pass gate transistor.
Claim 2
Dependent Claim
221 words
A fuse circuit for an integrated circuit device, comprising: a non-volatile programmable memory element having two programmed states; a programming circuit coupled to said memory element for programming said memory element in response to a programming control signal; a read circuit coupled to said memory element for detecting the programmed state of said programming circuit and for generating a low voltage level for one of said two programmed states and a high voltage level for the other of said programmed states; and a pass transistor coupled to said read circuit switchable from an open to a closed condition in response to a change in output voltage level of said read circuit; wherein a NOR gate is used for forcing the output of said read circuit to zero in response to a SPOR input signal to said NOR gate; wherein said integrated circuit device includes a read line coupled to said read circuit through a read pass gate transistor which is turned off during a write or programming mode or in response to a SPOR signal being high; and wherein said read circuit includes a transistor coupled between supply voltage V DD and a read end of a source to a drain path of said read pass gate transistor and responsive to conduct on the opening of said read pass gate transistor.
Claim 3
Dependent Claim
46 words
A fuse circuit according to claim 1, wherein said read circuit includes a second transistor coupled between V DD and said read end and responsive to an increase in voltage on said read end to turn on and maintain said read end at V DD .
Claim 4
Dependent Claim
205 words
A fuse circuit for an integrated circuit device, comprising: an electrically programmable read only memory cell; a programming circuit coupled to said memory cell for applying a predetermined voltage to a floating gate, a selection transistor gate and a floating gate transistor drain in response to a NSWRM control signal applied thereto; a read circuit coupled to said memory cell for detecting a programmed state of said memory cell and for generating a first voltage level for an unprogrammed state of said memory cell and a second voltage level for a programmed state of said memory cell; and a pass transistor coupled to said read circuit switchable from an open condition to a closed condition in response to a change in voltage level of an output of said read circuit; wherein said read circuit includes a pass gate transistor coupled to said read circuit and to said memory cell in the write or programming mode, includes a first transistor responsive to conduct on said pass gate transistor becoming non-conductive, includes a second transistor coupled between V DD supply voltage and said pass gate transistor responsive to conduct as long as either said pass gate transistor is conducting or, if not, said memory cell is non-conducting.
Claim 5
Dependent Claim
205 words
A fuse circuit for an integrated circuit device, comprising: an electrically programmable read only memory cell; a programming circuit coupled to said memory cell for applying a predetermined voltage to a floating gate, a selection transistor gate and a floating gate transistor drain in response to a NSWRM control signal applied thereto; a read circuit coupled to said memory cell for detecting a programmed state of said memory cell and for generating a first voltage level for an unprogrammed state of said memory cell and a second voltage level for a programmed state of said memory cell; and a pass transistor coupled to said read circuit switchable from an open condition to a closed condition in response to a change in voltage level of an output of said read circuit; wherein said read circuit includes a pass gate transistor coupled to said read circuit and to said memory cell in the write or programming mode, includes a first transistor responsive to conduct on said pass gate transistor becoming non-conductive, includes a second transistor coupled between V DD supply voltage and said pass gate transistor responsive to conduct as long as either said pass gate transistor is conducting or, if not, said memory cell is non-conducting.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |