Redundancy decoding circuit using n-channel transistors

Claim 2

In a decoding scheme for a redundant memory which includes a content addressable memory (CAM) for decoding an address signal to access locations in said redundant memory, an improvement in a decoding circuit, comprising: a first transistor; a second transistor coupled to said first transistor such that said first and second transistors are in series between a first node and a circuit return; a third transistor; a fourth transistor coupled to said third transistor such that said third and fourth transistors are in series between said first node and said return; gates of said first and third transistors being coupled to said CAM to receive a programmed signal and its complement; gates of said second and fourth transistors being coupled to receive said address signal and its complement; wherein said four transistors provide decoding of said address signal according to programming provided by said CAM.

Claim 3

The improvement defined by claim 1 further including a load device coupled between said first node and a supply voltage.

Claim 4

The improvement defined by claim 1 wherein said first node provides an output node for activating said redundant memory.

Claim 5

The improvement defined by claim 1 further including a fifth and sixth transistors coupled in series between said first node and a supply voltage and an output for activating said redundant memory is taken at a junction of said fifth and sixth transistors.

Claim 6

The improvement defined by claim 4 wherein said first, second, third and fourth transistors are n-channel transistors.

Claim 7

The improvement defined by claim 5 wherein said fifth transistor coupled to said first node is an n-channel transistor and said sixth transistor coupled to said supply voltage is a p-channel transistor.

Claim 8

In a decoding scheme for a redundant memory which includes a content addressable memory (CAM) for decoding an address signal to access locations in said redundant memory, an improvement in a decoding circuit, comprising: a first n-channel transistor having its source coupled to ground; a second n-channel transistor having its source coupled to the drain of said first n-channel transistor and its drain coupled to a first node; a third n-channel transistor having its source coupled to ground; a fourth n-channel transistor having its source coupled to the drain of said third n-channel transistor and its drain coupled to said first node; gates of said four n-channel transistors are coupled to receive a programmed signal, its complement, said address signal and its complement; wherein one of said address signal or its complement is provided to one of said first and second n-channel transistors and one of said programmed signal or its complement is provided to other of said first and second n-channel transistors; and wherein other of said address signal or its complement is provided to one of said third and fourth n-channel transistors and other of said programmed signal or its complement is provided to other of said third and fourth n-channel transistors; wherein said four n-channel transistors provide decoding of said address signal according to programming provided by said CAM.

Claim 9

In a decoding scheme for a redundant memory which includes a content addressable memory (CAM) for decoding an address signal to access locations in said redundant memory, an improvement in a decoding circuit, comprising: a first n-channel transistor having its source coupled to ground; a second n-channel transistor having its source coupled to the drain of said first n-channel transistor and its drain coupled to a first node; a third n-channel transistor having its source coupled to ground; a fourth n-channel transistor having its source coupled to the drain of said third n-channel transistor and its drain coupled to said first node; gates of said four n-channel transistors are coupled to receive a programmed signal, its complement, said address signal and its complement; wherein one of said address signal or its complement is provided to one of said first and second n-channel transistors and one of said programmed signal or its complement is provided to other of said first and second n-channel transistors; and wherein other of said address signal or its complement is provided to one of said third and fourth n-channel transistors and other of said programmed signal or its complement is provided to other of said third and fourth n-channel transistors; wherein said four n-channel transistors provide decoding of said address signal according to programming provided by said CAM.

Claim 10

The improvement defined by claim 7 further including a load device coupled between said first node and a supply voltage and said first node provides an output for activating said redundant memory.

Claim 11

The improvement defined by claim 8 wherein said decoding circuit provides a XNOR function.

Claim 12

The improvement defined by claim 8 wherein said load device is a p-channel transistor.

Claim 13

The improvement defined by claim 7 further including a fifth n-channel transistor and a p-channel transistor; said fifth n-channel transistor having its source coupled to said first node and its drain coupled to an output node; said p-channel transistor having its source coupled to a supply voltage and its drain coupled to said output node; and wherein said output node provides an output for activating said redundant memory.

Claim 14

The improvement defined by claim 11 wherein said fifth n-channel transistor is ratio biased with other said n-channel transistors to inhibit full voltage swings.

Claim 15

The improvement defined by claim 11 wherein said decoding circuit provides a XNOR function.