US5416783A
Expired / Lapsed
US
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Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor
Assignee: Apple Inc
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Filing: 1993-08-09
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Granted: 1995-05-16
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Expires: 2013-08-09
Abstract
Abstract A method and apparatus for generating pseudo-random numbers or for performing data compression in a data processor (12). In one form, the present invention generates pseudo-random numbers which are used to provide scan input data bits during built-in-self-test (BIST) scan testing. The present invention then performs data compression on the scan output data received back from the circuits under test (73-75). In one embodiment, the BIST scan testing of data processor (12) is performed in a special "background self-test mode". Central processing unit (CPU) 20 is used to generate the pseudo-random numbers and to perform the data compression. CPU 20 also functions as a standard CPU when in a normal operating mode.
Inventors
- 👤 James L. Broseghini
- 👤 James G. Viot
- 👤 Donald H. Lenhert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318335; G01R31/318385; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
127 words
A method for operating a data processor having an arithmetic logic unit, comprising the steps of: executing an instruction using said arithmetic logic unit while the data processor is in a normal operating mode; placing the data processor in a special test mode; while the data processor is in the special test mode, generating a plurality of pseudo-random bits using said arithmetic logic unit; while the data processor is in the special test mode, performing a scan test using the plurality of pseudo-random bits as at least a portion of a plurality of scan input data bits and producing a scan test result; and while the data processor is in the special test mode, performing data compression of the scan test result using said arithmetic logic unit.
Claim 2
Independent Claim
127 words
A method for operating a data processor having an arithmetic logic unit, comprising the steps of: executing an instruction using said arithmetic logic unit while the data processor is in a normal operating mode; placing the data processor in a special test mode; while the data processor is in the special test mode, generating a plurality of pseudo-random bits using said arithmetic logic unit; while the data processor is in the special test mode, performing a scan test using the plurality of pseudo-random bits as at least a portion of a plurality of scan input data bits and producing a scan test result; and while the data processor is in the special test mode, performing data compression of the scan test result using said arithmetic logic unit.
Claim 3
Dependent Claim
40 words
The method according to claim 1, wherein said step of placing the data processor in the special test mode comprises the step of: receiving an asserted signal at an integrated circuit bonding pad while the data processor is in reset.
Claim 4
Dependent Claim
34 words
The method according to claim 2, wherein said step of placing the data processor in the special test mode further comprises the step of: receiving a predetermined value at the integrated circuit bonding pad.
Claim 5
Dependent Claim
49 words
The method according to claim 1, wherein said step of generating a plurality of pseudo-random bits comprises the steps of: shifting a first value to produce a shifted first value and a feedback bit; and using the feedback bit as a first one of the plurality of pseudo-random bits.
Claim 6
Dependent Claim
47 words
The method according to claim 4, wherein said step of generating a plurality of pseudo-random bits further comprises the steps of: replicating the feedback bit to produce a replicated feedback value; and logically combining the replicated feedback value and a second value to produce an intermediate value.
Claim 7
Dependent Claim
34 words
The method according to claim 5, wherein said step of logically combining the replicated feedback value and the second value comprises the step of: logically ANDing the replicated feedback value and the second value.
Claim 8
Dependent Claim
28 words
The method according to claim 5, further comprising the steps of: storing the first value in a first register; and storing the second value in a second register.
Claim 9
Dependent Claim
37 words
The method according to claim 5, wherein said step of generating a plurality of pseudo-random bits further comprises the step of: logically combining the intermediate value and the shifted first value to produce a new first value.
Claim 10
Dependent Claim
33 words
The method according to claim 8, wherein said step of logically combining the intermediate value and the shifted first value comprises the step of: exclusive-ORing the intermediate value and the shifted first value.
Claim 11
Dependent Claim
121 words
An integrated circuit having an apparatus for performing scan testing, the apparatus comprising: first circuit means for logically combining a first binary value and a second binary value to produce an intermediate binary value; second circuit means, coupled to said first circuit means, said second circuit means exclusive-ORing the intermediate binary value and a third value; test control circuitry., coupled to said first circuit means and to said second circuit means, said test control circuitry controlling the scan testing; a first scan conductor, coupled to said first circuit means, said first scan conductor serially transferring a plurality of pseudo-random data bits; and a second scan conductor, coupled to said second circuit means, said second scan conductor serially transferring the third value.
Claim 12
Dependent Claim
121 words
An integrated circuit having an apparatus for performing scan testing, the apparatus comprising: first circuit means for logically combining a first binary value and a second binary value to produce an intermediate binary value; second circuit means, coupled to said first circuit means, said second circuit means exclusive-ORing the intermediate binary value and a third value; test control circuitry., coupled to said first circuit means and to said second circuit means, said test control circuitry controlling the scan testing; a first scan conductor, coupled to said first circuit means, said first scan conductor serially transferring a plurality of pseudo-random data bits; and a second scan conductor, coupled to said second circuit means, said second scan conductor serially transferring the third value.
Claim 13
Dependent Claim
34 words
The apparatus according to claim 10, wherein a first bit of the first value is a first bit of the plurality of pseudo-random data bits, and wherein the third value is a scan-out value.
Claim 14
Dependent Claim
27 words
The apparatus according to claim 10, wherein the apparatus further comprises: a circuit under test, coupled to said first scan conductor and to said second scan conductor.
Claim 15
Dependent Claim
28 words
The apparatus according to claim 10, wherein the apparatus further comprises: scan-input latches coupled to said first scan conductor; and scan-output latches, coupled to said second scan conductor.
Claim 16
Dependent Claim
15 words
The apparatus according to claim 10, wherein the apparatus further comprises: a plurality of registers.
Claim 17
Dependent Claim
19 words
The apparatus according to claim 10, wherein the apparatus further comprises: a counter, coupled to said first circuit means.
Claim 18
Dependent Claim
37 words
The apparatus according to claim 10, wherein the apparatus further comprises: a bus, coupled to said second circuit means; and a status bit, coupled to said bus, said status bit indicating if scan testing has been completed.
Claim 19
Dependent Claim
86 words
The apparatus according to claim 10, wherein the apparatus further comprises: a carry inhibit signal; wherein said first circuit means comprises: a logical ANDing circuit; and wherein said second circuit means comprises: a first adder circuit having an output, said first adder circuit receiving the carry inhibit signal; and a second adder circuit, having a first input coupled to said logical ANDing circuit, and having a second input coupled to the output of said first adder circuit, said second adder circuit receiving the carry inhibit signal.
Claim 20
Independent Claim
194 words
A method for generating a plurality of pseudo-random bits in a data processor, the data processor having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for performing an exclusive-OR function, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; shifting the first value to produce a plurality of electrical signals which represent a shifted first value and a plurality of electrical signals which represent a feedback value; logically combining the plurality of electrical signals which represent the feedback value and the plurality of electrical signals which represent the second value to produce a plurality of electrical signals which represent an intermediate value; exclusive-ORing the plurality of electrical signals which represent the intermediate value and the plurality of electrical signals which represent the shifted first value to produce a first pseudo-random bit; and generating a second pseudo-random bit.
Claim 21
Independent Claim
194 words
A method for generating a plurality of pseudo-random bits in a data processor, the data processor having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for performing an exclusive-OR function, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; shifting the first value to produce a plurality of electrical signals which represent a shifted first value and a plurality of electrical signals which represent a feedback value; logically combining the plurality of electrical signals which represent the feedback value and the plurality of electrical signals which represent the second value to produce a plurality of electrical signals which represent an intermediate value; exclusive-ORing the plurality of electrical signals which represent the intermediate value and the plurality of electrical signals which represent the shifted first value to produce a first pseudo-random bit; and generating a second pseudo-random bit.
Claim 22
Dependent Claim
18 words
The method according to claim 18, wherein all of said steps are performed during execution of an instruction.
Claim 23
Independent Claim
190 words
A method for performing data compression in a data processor, the data processor having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for performing an exclusive-OR function, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; shifting the first value to produce a plurality of electrical signals which represent a shifted first value and a plurality of electrical signals which represent a feedback value; logically combining the plurality of electrical signals which represent the feedback value and the plurality of electrical signals which represent the second value to produce a plurality of electrical signals which represent an intermediate value; and exclusive-ORing the plurality of electrical signals which represent the intermediate value, the plurality of electrical signals which represent the shifted first value, and a plurality of electrical signals which represent a third value.
Claim 24
Independent Claim
190 words
A method for performing data compression in a data processor, the data processor having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for performing an exclusive-OR function, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; shifting the first value to produce a plurality of electrical signals which represent a shifted first value and a plurality of electrical signals which represent a feedback value; logically combining the plurality of electrical signals which represent the feedback value and the plurality of electrical signals which represent the second value to produce a plurality of electrical signals which represent an intermediate value; and exclusive-ORing the plurality of electrical signals which represent the intermediate value, the plurality of electrical signals which represent the shifted first value, and a plurality of electrical signals which represent a third value.
Claim 25
Dependent Claim
18 words
The method according to claim 20, wherein all of said steps are performed during execution of an instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-15 | 1998-11-14 | 1999-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-15 | 2002-11-14 | 2003-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-15 | 2006-11-14 | 2007-05-16 | $7700.00 | Window Closed / Lapsed |