US4189716A
Expired / Lapsed
US
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Circuit for determining the number of ones in a binary signal
Assignee: AT&T Inc
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Filing: 1978-12-15
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Granted: 1980-02-19
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Expires: 1998-12-15
Abstract
Abstract The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.
Inventors
- 👤 Robert H. Krambeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:13
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/607
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
128 words
A circuit arrangement for counting the number of like binary bits in a binary word of x≧8 bits, said arrangement comprising at least first and second combinatorial logic circuits including y 1 >3≦x/2 and y 2 ≦x-y 1 factorial logic elements, respectively, and input means adapted responsive to external signals representative of said binary word to apply to said elements of said first and second circuits y 1 and y 2 bits of said binary word, respectively, said circuit arrangement also including an adder circuit for adding together two N>3 bit words produced by said logic circuits, where N equals the larger of y 1 and y 2 , each of said first and second circuits being adapted to apply an N bit word to said adder circuit.
Claim 2
Dependent Claim
128 words
A circuit arrangement for counting the number of like binary bits in a binary word of x≧8 bits, said arrangement comprising at least first and second combinatorial logic circuits including y 1 >3≦x/2 and y 2 ≦x-y 1 factorial logic elements, respectively, and input means adapted responsive to external signals representative of said binary word to apply to said elements of said first and second circuits y 1 and y 2 bits of said binary word, respectively, said circuit arrangement also including an adder circuit for adding together two N>3 bit words produced by said logic circuits, where N equals the larger of y 1 and y 2 , each of said first and second circuits being adapted to apply an N bit word to said adder circuit.
Claim 3
Dependent Claim
14 words
A circuit arrangement in accordance with claim 1 wherein y 1 =y 2 =x/2.
Claim 4
Dependent Claim
15 words
A circuit arrangement in accordance with claim 2 defined in a semiconductor integrated circuit chip.
Claim 5
Dependent Claim
32 words
A circuit arrangement in accordance with claim 1 where y 1 =x/2>y 2 and said second circuit is adapted to add Z zeroes to the output thereof such that y 2 +Z=N.
References Cited (Backward Citations)
US3656109A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-18 | 1983-08-20 | 1984-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-18 | 1987-08-20 | 1988-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-18 | 1991-08-20 | 1992-02-19 | $7700.00 | Window Closed / Lapsed |