Method and apparatus for generating pseudo-random numbers

Claim 1

An apparatus for generating pseudo-random numbers, comprising: a first circuit which logically combines a first binary value and a second binary value to produce an intermediate binary value; and a second circuit which is coupled to said first circuit, which receives the intermediate binary value from said first circuit, and which produces a binary bit which has a first logic state if the intermediate binary value contains an odd number of ones and which has a second logic state if the intermediate binary value contains an even number of ones, said second circuit using the binary bit to determine a bit of a pseudo-random number.

Claim 2

An apparatus for generating pseudo-random numbers, comprising: a first circuit which logically combines a first binary value and a second binary value to produce an intermediate binary value; and a second circuit which is coupled to said first circuit, which receives the intermediate binary value from said first circuit, and which produces a binary bit which has a first logic state if the intermediate binary value contains an odd number of ones and which has a second logic state if the intermediate binary value contains an even number of ones, said second circuit using the binary bit to determine a bit of a pseudo-random number.

Claim 13

A method for generating a pseudo-random number value in a data processing system, the data processing system having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for producing a control signal, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; logically combining the first plurality of electrical signals which represent the first value and the second plurality of electrical signals which represent a second value to produce an intermediate value; placing the control signal in a first logic state if a number of ones in a binary representation of the intermediate value is odd; and generating a pseudo-random number value based upon the first value and the control signal.

Claim 14

A method for generating a pseudo-random number value in a data processing system, the data processing system having a plurality of registers and having a circuit for performing a logical combination function coupled to a circuit for producing a control signal, the method comprising the steps of: transferring, from a first one of the plurality of registers to a first bus, a first plurality of electrical signals which represent a first value; transferring, from a second one of the plurality of registers to a second bus, a second plurality of electrical signals which represent a second value; logically combining the first plurality of electrical signals which represent the first value and the second plurality of electrical signals which represent a second value to produce an intermediate value; placing the control signal in a first logic state if a number of ones in a binary representation of the intermediate value is odd; and generating a pseudo-random number value based upon the first value and the control signal.

Claim 24

A method for operating a digital data processor comprising the steps of: decoding an instruction; and performing, in response to said decoding of the instruction, the steps of: 1) retrieving a first value from a first storage circuit; 2) retrieving a second value from a second storage circuit; 3) logically combining the first value and the second value to produce an intermediate value; 4) placing a binary bit in a first logic state if a number of ones in a binary representation of the intermediate value is odd; and 5) generating a pseudo-random number based upon the first value and the binary bit.

Claim 25

A method for operating a digital data processor comprising the steps of: decoding an instruction; and performing, in response to said decoding of the instruction, the steps of: 1) retrieving a first value from a first storage circuit; 2) retrieving a second value from a second storage circuit; 3) logically combining the first value and the second value to produce an intermediate value; 4) placing a binary bit in a first logic state if a number of ones in a binary representation of the intermediate value is odd; and 5) generating a pseudo-random number based upon the first value and the binary bit.

Claim 29

An apparatus for generating pseudo-random numbers, comprising: first storage circuit for storing a first binary value; second storage circuit for storing a second binary value; ANDing circuit for logically ANDing the first binary value and the second binary value to produce an intermediate binary value, said ANDing circuit being coupled to said first storage circuit and said second storage circuit; and logic circuit for receiving the intermediate binary value from said ANDing circuit and for placing a binary bit in a first logic state if the intermediate binary value contains an odd number of ones, said logic circuit using the first binary value and the binary bit to generate a pseudo-random number.

Claim 30

An apparatus for generating pseudo-random numbers, comprising: first storage circuit for storing a first binary value; second storage circuit for storing a second binary value; ANDing circuit for logically ANDing the first binary value and the second binary value to produce an intermediate binary value, said ANDing circuit being coupled to said first storage circuit and said second storage circuit; and logic circuit for receiving the intermediate binary value from said ANDing circuit and for placing a binary bit in a first logic state if the intermediate binary value contains an odd number of ones, said logic circuit using the first binary value and the binary bit to generate a pseudo-random number.

Claim 31

An apparatus for generating a pseudo-random number, comprising: a storage circuit for storing a previously generated pseudo-random number; a programmable register circuit for storing a mask value; and circuitry, coupled to said storage circuit for receiving the previously generated pseudo-random number and coupled to said programmable register circuit for receiving the mask value, said circuitry using the mask value to select which bits of the previously generated pseudo-random number are masked, said circuitry generating the pseudo-random number based upon the previously generated pseudo-random number and the mask value.

Claim 32

An apparatus for generating a pseudo-random number, comprising: a storage circuit for storing a previously generated pseudo-random number; a programmable register circuit for storing a mask value; and circuitry, coupled to said storage circuit for receiving the previously generated pseudo-random number and coupled to said programmable register circuit for receiving the mask value, said circuitry using the mask value to select which bits of the previously generated pseudo-random number are masked, said circuitry generating the pseudo-random number based upon the previously generated pseudo-random number and the mask value.