Built-in self-test circuit

Claim 2

An input register for an integrated circuit, said integrated circuit including a plurality of input pads and an internal logic block, said input register comprising: a programmable polynomial function generator for generating successive pseudo random data patterns to be supplied to said internal logic block, said programmable polynomial function generator implementing a polynomial to determine a sequence for the successive pseudo random patterns; and logic circuitry connected to receive the output of said programmable polynomial function generator for selecting a feedback signal to be provided back to said programmable polynomial function generator to select a characteristic polynomial and a polynomial bit length to be implemented by said programmable polynomial function generator.

Claim 3

The input register according to claim 1, further comprising: compare logic circuitry connected to receive the output of said programmable polynomial function generator for generating a stop count signal upon the receipt of a predetermined bit pattern from said polynomial function generator.

Claim 6

In an input register for an integrated circuit, said input register comprising a plurality of input cells connected together to form a pseudo random pattern generator and means connected to receive said pseudo random data for generating a stop count signal upon the receipt of a predetermined stop pattern, a method for generating a predetermined number of pseudo random data patterns, said method comprising the steps of: determining a start value required to produce said predetermined number of pseudo random data patterns concluding with said predetermined stop pattern, said step of determining said start value including the steps of: forming a computer model of the reciprocal of said LFSR for generating an inverse succession of pseudo random data patterns; counting through said inverse succession of pseudo random data patterns beginning with said predetermined stop pattern for said predetermined number of pseudo random data patterns to arrive at said start value; and preloading said LFSR with said start value.

Claim 7

In an input register for an integrated circuit, said input register comprising a plurality of input cells connected together to form a pseudo random pattern generator and means connected to receive said pseudo random data for generating a stop count signal upon the receipt of a predetermined stop pattern, a method for generating a predetermined number of pseudo random data patterns, said method comprising the steps of: determining a start value required to produce said predetermined number of pseudo random data patterns concluding with said predetermined stop pattern, said step of determining said start value including the steps of: forming a computer model of the reciprocal of said LFSR for generating an inverse succession of pseudo random data patterns; counting through said inverse succession of pseudo random data patterns beginning with said predetermined stop pattern for said predetermined number of pseudo random data patterns to arrive at said start value; and preloading said LFSR with said start value.