US5029171A
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Test vector generation system
Assignee: Raytheon Co
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Filing: 1989-05-25
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Granted: 1991-07-02
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Expires: 2009-05-25
Abstract
Abstract A test pattern data generator 16 may be made to create and generate all of the unique test vectors associated with it. These test vectors may have an arbitrarily selected programmable length 26(a-d) and may be generated in an arbitrarily selected programmable quantity 28(a-d). Furthermore, a unique test vector may be generated in a number of clock periods approximately equal to the number of shift registers (156, 158) contained in a scan or application interface unit 20. All these features are accomplished by initially placing a seed initialization value in the test pattern generator 16 and having the test pattern data generator cycle through a number of states, the second state of the test pattern generation being inputted to a seed register 12. The contents of the seed register 12 are used as the seed initialization value for the second test vector to be generated by the generator 16. This process is continued until all of the unique test vectors have been created. This invention also allows for test partitioning whereby the contents of the seed register 12 may be stored for a period of time and a complete test, entailing the creation and generation of a complete set of unique test vectors, may be partitioned in time, into a series of tests containing smaller numbers of these unique test vectors.
Inventors
- 👤 Gene W. Lee
- 👤 George D. Underwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/319; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
141 words
A test vector generation system for generating test data to a logic system wherein said logic system contains a plurality of scan registers having an input and output, said test vector generation system comprising: (a) test pattern data generation means, having an input and output, for creating and generating a sequence of test vectors, each of said test vectors being created from a seed initialization value; (b) means for coupling said output of said test pattern data generation means to said input of said plurality of scan registers; and (c) control means, in communication with both said test pattern data generation means and said scan registers, for identifying and storing the seed initialization values associated with each of said test vectors whereby, substantially all of the test vectors associated with said test pattern data generation means may be created and generated.
Claim 2
Dependent Claim
141 words
A test vector generation system for generating test data to a logic system wherein said logic system contains a plurality of scan registers having an input and output, said test vector generation system comprising: (a) test pattern data generation means, having an input and output, for creating and generating a sequence of test vectors, each of said test vectors being created from a seed initialization value; (b) means for coupling said output of said test pattern data generation means to said input of said plurality of scan registers; and (c) control means, in communication with both said test pattern data generation means and said scan registers, for identifying and storing the seed initialization values associated with each of said test vectors whereby, substantially all of the test vectors associated with said test pattern data generation means may be created and generated.
Claim 3
Dependent Claim
144 words
A test vector generation system for generating test data to a logic system wherein said logic system contains a plurality of scan registers having an input and output, said test vector generation system comprises: (a) test pattern data generation means, having an input and output, for creating and generating a sequence of test vectors, each of said test vectors being created from a seed initialization value; (b) means for coupling said output of said test pattern data generation means to said input of said plurality of scan registers; (c) control means, in communication with both said test pattern data generation means and said scan registers, for identifying said seed initialization values associated with each of said test vectors and for coupling said seed initialization values to said test pattern data generation means at selected intervals of time in order to allow for test partitioning.
Claim 4
Dependent Claim
144 words
A test vector generation system for generating test data to a logic system wherein said logic system contains a plurality of scan registers having an input and output, said test vector generation system comprises: (a) test pattern data generation means, having an input and output, for creating and generating a sequence of test vectors, each of said test vectors being created from a seed initialization value; (b) means for coupling said output of said test pattern data generation means to said input of said plurality of scan registers; (c) control means, in communication with both said test pattern data generation means and said scan registers, for identifying said seed initialization values associated with each of said test vectors and for coupling said seed initialization values to said test pattern data generation means at selected intervals of time in order to allow for test partitioning.
Claim 5
Dependent Claim
21 words
A test vector generation system of claim 1 wherein said test pattern data generation means comprises a linear feedback shift register.
Claim 6
Dependent Claim
99 words
The test vector generation system of claim 3 wherein said linear feedback shift register comprises: (a) data multiplexing means, having an input and output, for receiving data; (b) flip-flop means, having an input and output, for receiving and storing data; (c) first means for coupling said input of said data multiplexing means to said control means; (d) second means for coupling said output of said data multiplexing means to said input of said flip-flop means; and (e) third means for coupling said output of said flip-flop means to said control means and to said logic system to be tested.
Claim 7
Dependent Claim
21 words
A test vector generation system of claim 2 wherein said test pattern data generation means comprises a linear feedback shift register.
Claim 8
Dependent Claim
99 words
The test vector generation system of claim 5 wherein said linear feedback shift register comprises: (a) data multiplexing means, having an input and output, for receiving data; (b) flip-flop means, having an input and output, for receiving and storing data; (c) first means for coupling said input of said data multiplexing means to said control means; (d) second means for coupling said output of said data multiplexing means to said input of said flip-flop means; and (e) third means for coupling said output of said flip-flop means to said control means and to said logic system to be tested.
Claim 9
Dependent Claim
204 words
The test vector generation system of claim 1 wherein said control means comprises: (a) first binary counter means, having an input and output, for programming the length to be associated with said test vectors, said test vector length to be substantially defined by a signal coupled to said input thereof; (b) second binary counter means, having an input and output, for programming the quantity of said unique test vectors to be created by said test pattern data generation means, said test vector quantity to be substantially defined by a signal coupled to said input thereof; (c) seed register means, having an input and output, for storing said seed initialization values; (d) first coupling means for coupling said output of said first binary counter means to said input of said test pattern data generation means; (e) second coupling means for coupling said output of said second binary counter means to said input of said test pattern generation means; (f) third coupling means for coupling said input of said seed register means to said output of said test pattern data generation means; and (g) fourth coupling means for coupling said output of said seed register means to said input of said test pattern data generation means.
Claim 10
Dependent Claim
68 words
The test vector generation system of claim 7 wherein said control means further comprises means for applying a clock signal having a plurality of periods for generally controlling the flow of data within said test vector generation system, wherein each of said test vectors can be generated within a number of said clock periods approximately equal to the number of registers contained within said plurality of scan registers.
Claim 11
Dependent Claim
17 words
The test vector generation system of claim 7 wherein said fourth coupling means comprises a data multiplexer.
Claim 12
Dependent Claim
204 words
The test vector generation system of claim 2 wherein said control means comprises: (a) first binary counter means, having an input and output, for programming the length to be associated with said test vectors, said test vector length to be substantially defined by a signal coupled to said input thereof; (b) second binary counter means, having an input and output, for programming the quantity of said unique test vectors to be created by said test pattern data generation means, said test vector quantity to be substantially defined by a signal coupled to said input thereof; (c) seed register means, having an input and output, for storing said seed initialization values; (d) first coupling means for coupling said output of said first binary counter means to said input of said test pattern data generation means; (e) second coupling means for coupling said output of said second binary counter means to said input of said test pattern generation means; (f) third coupling means for coupling said input of said seed register means to said output of said test pattern data generation means; and (g) fourth coupling means for coupling said output of said seed register means to said input of said test pattern data generation means.
Claim 13
Dependent Claim
68 words
The test vector generation system of claim 10 wherein said control means further comprises means for applying a clock signal having a plurality of periods for generally controlling the flow of data within said test vector generation system, wherein each of said test vectors can be generated within a number of said clock periods approximately equal to the number of registers contained within said plurality of scan registers.
Claim 14
Dependent Claim
17 words
The test vector generation system of claim 10 wherein said fourth coupling means comprises a data multiplexer.
Claim 15
Independent Claim
294 words
A method for generating substantially all of the unique test vectors associated with a test pattern data generation, said method comprising the steps of: (a) inputting a test vector initialization seed into a seed register means, having an input and output, for storing data; (b) inputting said test vector initialization seed, from said seed register means, into test pattern data generation means for creating and generating a sequence of test vectors, said test pattern data generation means, having an input and output, cycling through a series of states such that a single bit of data is output during each cycle and wherein, said test vector initialization seed defines the first state of said test pattern data generation means wherein said state is generally defined by the data contained within said test pattern data generation means at a given time; (c) coupling the output of said test pattern data generation means to an input of a scan data register means for storing data said scan data register means having an output and containing a plurality of data registers; (d) inputting the second state of said test pattern data generation means into said seed register means; (e) coupling the output of said scan register means to a combinational logic system to be tested, said coupling being accomplished only when approximately every register of said scan register means contains data received from said test pattern data generation means and wherein said sequence of data contained within said registers of said scan register means is defined to be a single test vector; and (f) coupling the output of said seed register means to said test pattern data generation means wherein said output is defined to be the vector initialization seed of the next test vector to be generated.
Claim 16
Independent Claim
294 words
A method for generating substantially all of the unique test vectors associated with a test pattern data generation, said method comprising the steps of: (a) inputting a test vector initialization seed into a seed register means, having an input and output, for storing data; (b) inputting said test vector initialization seed, from said seed register means, into test pattern data generation means for creating and generating a sequence of test vectors, said test pattern data generation means, having an input and output, cycling through a series of states such that a single bit of data is output during each cycle and wherein, said test vector initialization seed defines the first state of said test pattern data generation means wherein said state is generally defined by the data contained within said test pattern data generation means at a given time; (c) coupling the output of said test pattern data generation means to an input of a scan data register means for storing data said scan data register means having an output and containing a plurality of data registers; (d) inputting the second state of said test pattern data generation means into said seed register means; (e) coupling the output of said scan register means to a combinational logic system to be tested, said coupling being accomplished only when approximately every register of said scan register means contains data received from said test pattern data generation means and wherein said sequence of data contained within said registers of said scan register means is defined to be a single test vector; and (f) coupling the output of said seed register means to said test pattern data generation means wherein said output is defined to be the vector initialization seed of the next test vector to be generated.
Claim 17
Dependent Claim
21 words
The method of claim 13 wherein said test vector generation occurs at selected intervals of time to allow for test partitioning.
Claim 18
Dependent Claim
48 words
The method of claim 13 wherein a clock signal having a plurality of periods controls the flow of data, and wherein a unique test vector may be generated within a number of clock periods approximately equal to the number of said registers contained within said scan register means.
Claim 19
Dependent Claim
28 words
The method of claim 13 wherein the step of inputting said test vector initialization into test pattern data generation means includes inputting into a linear feedback shift register.
Claim 20
Dependent Claim
115 words
The method of claim 16 wherein the step of inputting into the linear feedback shift register comprises: (a) incorporating data multiplexing means for receiving data, having an input and output; (b) incorporating flip-flop means for receiving and storing data, having an input and output; (c) incorporating first means for coupling said input of said data multiplexing means to said output of said seed register means; (d) incorporating second means for coupling said output of said data multiplexing means to said input of said flip-flop means; and (e) incorporating third means for coupling said output of said flip-flop means to said input of said seed register means and to said combinational logic system to be tested.
Claim 21
Dependent Claim
134 words
A test vector generation system comprising: (a) a linear feedback shift register means for creating and generating a sequence of test vectors wherein said test vectors are generated from an initialization seed value; (b) scan register means, containing a plurality of data registers, for receiving and transferring data; (c) means for applying a clock signal having a plurality of periods for generally controlling the flow of data within said test vector generation system whereby substantially all unique test vectors associated with said linear feedback shift register means may be generated within a number of said clock periods approximately equal to the number of registers contained within said scan register means; (d) seed register means having an input and output for storing said initialization seed values; and (e) control means for identifying said seed values.
Claim 22
Dependent Claim
134 words
A test vector generation system comprising: (a) a linear feedback shift register means for creating and generating a sequence of test vectors wherein said test vectors are generated from an initialization seed value; (b) scan register means, containing a plurality of data registers, for receiving and transferring data; (c) means for applying a clock signal having a plurality of periods for generally controlling the flow of data within said test vector generation system whereby substantially all unique test vectors associated with said linear feedback shift register means may be generated within a number of said clock periods approximately equal to the number of registers contained within said scan register means; (d) seed register means having an input and output for storing said initialization seed values; and (e) control means for identifying said seed values.
Claim 23
Dependent Claim
26 words
The test vector generation system of claim 18 wherein said test vector generation occurs at selected intervals of time in order to allow for test partitioning.
Claim 24
Dependent Claim
108 words
The test vector generation system of claim 18 wherein said linear feedback shift register means comprises: (a) data multiplexing means for receiving data, having an input and output; (b) flip-flop means for receiving and storing data, having an input and output; (c) first means for coupling said input of said data multiplexing means to said output of said seed register means; (d) second means for coupling said output of said data multiplexing means to said input of said flip-flop means; and (e) third means for coupling said output of said flip-flop means to said input of said seed register means and to a logic system to be tested.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |