US5409849A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a compound semiconductor device having gate electrode self-aligned to source and drain electrodes
Assignee: Toshiba Corp
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Filing: 1993-05-07
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Granted: 1995-04-25
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Expires: 2013-05-07
Abstract
Abstract According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.
Inventors
- 👤 Yoshihiro Kishita
- 👤 Masanori Ochi
- 👤 Souichi Imamura
- 👤 Toshikazu Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/015; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/20; H10D64/27; H10D64/311; H10D64/411
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
177 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an active layer in a semiconductor substrate; forming a source electrode and a drain electrode on said active layer; forming a groove in a portion of said active layer, said groove being between said source electrode and said drain electrode, wherein said groove forming step forms a first damage layer in said active layer; wet-etching exposed surfaces of said active layer, thereby removing said first damage layer in said active layer; forming an insulating layer on a side wall of said groove, a side wall of said source electrode and a side wall of said drain electrode, by anisotropic etching, wherein said insulating layer forming step forms a second damage layer in said active layer; wet-etching a portion of said active layer, exposing a bottom of said groove, thereby removing said second damage layer in said active layer; and forming a gate electrode on said portion of said active layer exposed in said bottom of said groove, after removing said first and second damage layers.
Claim 2
Independent Claim
177 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an active layer in a semiconductor substrate; forming a source electrode and a drain electrode on said active layer; forming a groove in a portion of said active layer, said groove being between said source electrode and said drain electrode, wherein said groove forming step forms a first damage layer in said active layer; wet-etching exposed surfaces of said active layer, thereby removing said first damage layer in said active layer; forming an insulating layer on a side wall of said groove, a side wall of said source electrode and a side wall of said drain electrode, by anisotropic etching, wherein said insulating layer forming step forms a second damage layer in said active layer; wet-etching a portion of said active layer, exposing a bottom of said groove, thereby removing said second damage layer in said active layer; and forming a gate electrode on said portion of said active layer exposed in said bottom of said groove, after removing said first and second damage layers.
Claim 3
Dependent Claim
22 words
A method of manufacturing a semiconductor device according to claim 1, wherein said second damage layer is caused by said anisotropic etching.
Claim 4
Dependent Claim
20 words
A method of manufacturing a semiconductor device according to claim 2, wherein said anisotropic etching is a reactive ion etching.
Claim 5
Dependent Claim
19 words
A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate comprises a compound semiconductor.
Claim 6
Dependent Claim
17 words
A method of manufacturing a semiconductor device according to claim 4, wherein said compound semiconductor comprises GaAs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |