US4731339A
Expired / Lapsed
US
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Process for manufacturing metal-semiconductor field-effect transistors
Assignee: Conexant Systems LLC
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Filing: 1986-08-25
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Granted: 1988-03-15
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Expires: 2006-08-25
Abstract
Abstract A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N - layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N + region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N + region, the N + /N - interface, and the exposed portion of the N - layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N - layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.
Inventors
- 👤 Frank J. Ryan
- 👤 Man-Chung F. Chang
- 👤 Dennis A. Williams
- 👤 Richard P. Vahrenkamp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
227 words
A method of forming a metal-semiconductor field-effect transistor (MESFET) comprising the steps of: providing a semiconductor having a dielectric film; implanting ions through said dielectric film to form an N - layer in a selected area of said semiconductor; forming a dummy gate on said dielectric film over said N - layer using a single-level photoresist process; implanting ions through said dielectric film to form an N + region in said selected area while using said dummy gate to mask said N - layer and retain an N - layer for the gate of said MESFET; reducing the length of said dummy gate by reactive ion etching; depositing an SiO x dielectric on said dielectric film covering said N + implanted region and on the portion of said N - layer not covered by said dummy gate, while using said dummy gate to mask the underlying portion of said N - layer; lifting off said dummy gate; annealing said N - layer and said N + region; etching source and drain openings in said dielectric film and in said SiO x dielectric; depositing ohmic metal contacts in said openings to form the source and drain of said MESFET; recessing said N - layer by exposing it to a reactive ion etch plasma to obtain the desired threshold voltage; and depositing gate metallization on said N - layer.
Claim 2
Independent Claim
227 words
A method of forming a metal-semiconductor field-effect transistor (MESFET) comprising the steps of: providing a semiconductor having a dielectric film; implanting ions through said dielectric film to form an N - layer in a selected area of said semiconductor; forming a dummy gate on said dielectric film over said N - layer using a single-level photoresist process; implanting ions through said dielectric film to form an N + region in said selected area while using said dummy gate to mask said N - layer and retain an N - layer for the gate of said MESFET; reducing the length of said dummy gate by reactive ion etching; depositing an SiO x dielectric on said dielectric film covering said N + implanted region and on the portion of said N - layer not covered by said dummy gate, while using said dummy gate to mask the underlying portion of said N - layer; lifting off said dummy gate; annealing said N - layer and said N + region; etching source and drain openings in said dielectric film and in said SiO x dielectric; depositing ohmic metal contacts in said openings to form the source and drain of said MESFET; recessing said N - layer by exposing it to a reactive ion etch plasma to obtain the desired threshold voltage; and depositing gate metallization on said N - layer.
Claim 3
Dependent Claim
26 words
The method as claimed in claim 1 wherein said semiconductor comprises semi-insulating gallium arsenide and said dielectric film comprises silicon nitride sputtered on said gallium arsenide.
Claim 4
Dependent Claim
32 words
The method as claimed in claim 1 wherein said reactive ion etch plasma comprises a mixture of CF 4 and H 2 or a mixture of CF 4 and O 2 .
Claim 5
Dependent Claim
47 words
The method as claimed in claim 1 wherein said step of recessing said N - layer comprises first exposing test samples to a reactive ion etch plasma at various power levels and for various times in order to determine a relationship between power, time and threshold voltage.
Claim 6
Dependent Claim
16 words
The method as claimed in claim 1 wherein said semiconductor comprises a high electron mobility semiconductor.
Claim 7
Independent Claim
206 words
A method of forming a metal-semiconductor field-effect transistor (MESFET) comprising the steps of: providing a semiconductor having a dielectric film; implanting ions through said dielectric film to form an N - layer in a selected area of said semiconductor; forming a dummy gate on said dielectric film over said N - layer using a single-level photoresist process; implanting ions through said dielectric film to form an N + region in said selected area while using said dummy gate to mask said N - layer and retain an N - layer for the gate of said MESFET; reducing the length of said dummy gate by reactive ion etching; depositing an SiO x dielectric on said dielectric film covering said N + implanted region and on the portion of said N - layer not covered by said dummy gate, while using said dummy gate to mask the underlying portion of said N - layer; lifting off said dummy gate; annealing said N - layer and said N + region; etching source and drain openings in said dielectric film and in said SiO x dielectric; depositing ohmic metal contacts in said openings to form the source and drain of said MESFET; depositing gate metallization on said N - layer.
Claim 8
Independent Claim
206 words
A method of forming a metal-semiconductor field-effect transistor (MESFET) comprising the steps of: providing a semiconductor having a dielectric film; implanting ions through said dielectric film to form an N - layer in a selected area of said semiconductor; forming a dummy gate on said dielectric film over said N - layer using a single-level photoresist process; implanting ions through said dielectric film to form an N + region in said selected area while using said dummy gate to mask said N - layer and retain an N - layer for the gate of said MESFET; reducing the length of said dummy gate by reactive ion etching; depositing an SiO x dielectric on said dielectric film covering said N + implanted region and on the portion of said N - layer not covered by said dummy gate, while using said dummy gate to mask the underlying portion of said N - layer; lifting off said dummy gate; annealing said N - layer and said N + region; etching source and drain openings in said dielectric film and in said SiO x dielectric; depositing ohmic metal contacts in said openings to form the source and drain of said MESFET; depositing gate metallization on said N - layer.
Claim 9
Dependent Claim
39 words
The method as claimed in claim 6, wherein said step of implanting ions to form an N - layer comprises implanting Se ions, and said step of implanting ions to form an N + region comprises implanting Si ions.
Claim 10
Dependent Claim
15 words
The method as claimed in claim 6, wherein said step of etching comprises dry etching.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-15 | 1991-09-14 | 1992-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-15 | 1995-09-14 | 1996-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-15 | 1999-09-14 | 2000-03-15 | $7700.00 | Window Closed / Lapsed |