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US4981809A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a mask pattern for the production of transistor

Assignee: Sumitomo Electric Industries Ltd
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Filing: 1988-08-10
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Granted: 1991-01-01
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Expires: 2008-08-10
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Abstract

Abstract A method of making a fine mask pattern suitable for making a compound semiconductor device in which a source and drain regions are formed on both sides of a groove defined in a substrate and both regions are separated from the side walls of the groove by predetermined intervals through a first region with a depth shallower than the groove. A second region is formed between the source and drain region with a depth deeper than said groove. A gate electrode is formed on the surface of the second region in the groove for Schottky contacting with the upper surface of the second region.

Inventors

  • 👤 Fujihira Mitsuaki
  • 👤 Masanori Nishiguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 02:36
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/221; H10D10/01; H10D10/031; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D30/80; H10D30/87; H10D30/877; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10P; H10P76/00; H10P76/20; H10P76/204; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/133

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 89 words
A method for forming a mask pattern comprising the steps of: depositing a mask layer made of low softening point materials on a surface of a semiconductor substrate; forming an opening in the mask layer; etching the semiconductor substrate through the opening in the mask layer; and heating the semiconductor substrate with the mask layer, thereby softening and fluidifying the mask layer so as to cause a part of the mask layer proximate the opening to expand toward the opening so as to narrow a width of the opening.
Claim 2
Independent Claim 89 words
A method for forming a mask pattern comprising the steps of: depositing a mask layer made of low softening point materials on a surface of a semiconductor substrate; forming an opening in the mask layer; etching the semiconductor substrate through the opening in the mask layer; and heating the semiconductor substrate with the mask layer, thereby softening and fluidifying the mask layer so as to cause a part of the mask layer proximate the opening to expand toward the opening so as to narrow a width of the opening.
Claim 3
Independent Claim 277 words
A method for producing a compound semiconductor device , said method comprising the steps of: implanting impurities of a predetermined conductive type with high density in regions for forming a source region and a drain region in a compound semiconductor substrate; implanting impurities of the same predetermined conductive type with high density in a shallow region including a portion between the source and the drain regions so as to form a first region; implanting impurities of the same predetermined conductive type with low density in a same region as the first region and being deeper than the first region but shallower than the source and drain regions so as to form a second region; depositing a mask layer made of low softening point materials on a surface of a semiconductor substrate; forming an opening in the mask layer; etching the semiconductor substrate through the opening in the mask layer so as to form a groove insulation layer with a depth deeper than that of the first region and shallower than that of the second region, in a middle portion between the source and drain regions, remaining a predetermined width of the first regions in both sides of the groove, one end portion of each first region being in contact with the source and drain regions respectively; heating the compound semiconductor substrate so as to soften and fluidify the insulation layers so as to have the insulation layers hang down from the upper portions of the first regions int the groove; and forming a gate electrode in Schottky contact with the upper surface of the second region on the bottom of the groove exposed between the insulation layers.
Claim 4
Independent Claim 277 words
A method for producing a compound semiconductor device , said method comprising the steps of: implanting impurities of a predetermined conductive type with high density in regions for forming a source region and a drain region in a compound semiconductor substrate; implanting impurities of the same predetermined conductive type with high density in a shallow region including a portion between the source and the drain regions so as to form a first region; implanting impurities of the same predetermined conductive type with low density in a same region as the first region and being deeper than the first region but shallower than the source and drain regions so as to form a second region; depositing a mask layer made of low softening point materials on a surface of a semiconductor substrate; forming an opening in the mask layer; etching the semiconductor substrate through the opening in the mask layer so as to form a groove insulation layer with a depth deeper than that of the first region and shallower than that of the second region, in a middle portion between the source and drain regions, remaining a predetermined width of the first regions in both sides of the groove, one end portion of each first region being in contact with the source and drain regions respectively; heating the compound semiconductor substrate so as to soften and fluidify the insulation layers so as to have the insulation layers hang down from the upper portions of the first regions int the groove; and forming a gate electrode in Schottky contact with the upper surface of the second region on the bottom of the groove exposed between the insulation layers.
Claim 5
Dependent Claim 33 words
The method for producing a compound semiconductor device according to claim 2, wherein in the impurity implanting step, the first and second regions are formed after the source and drain regions are formed.
Claim 6
Dependent Claim 33 words
The method for producing a compound semiconductor device according to claim 2, wherein in the impurity implanting step, the source and drain regions are formed after the first and second regions are formed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-12-31 1994-07-02 1995-01-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-12-31 1998-07-02 1999-01-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-12-31 2002-07-02 2003-01-01 $7700.00 Window Closed / Lapsed

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