US4784967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a field-effect transistor with a self-aligned gate
Assignee: Nokia Bell Labs
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Filing: 1986-12-19
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Granted: 1988-11-15
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Expires: 2006-12-19
Abstract
Abstract A method of fabricating a field-effect transistor is disclosed wherein only two masking steps are used in the development of the device. The semiconductor wafer used in the process has a non-alloyed contact at its top surface, that is, a contact which does not require alloying temperatures in excess of 200 degrees C. The first mask is used to create conventional mesa structures which isolate each individual field-effect transistor from its adjacent neighbors. A second mask is utilized to define the source and drain electrodes and also to create a gap through which the gate electrode structure is fabricated. By using a single mask for creation of both the source and drain electrodes and the gate structure, very close tolerances are obtained between the gate structure and the source and drain regions.
Inventors
- 👤 John E. Cunningham
- 👤 Erdmann F. Schubert
- 👤 Won-Tien Tsang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/692; Y; Y10; Y10S; Y10S148/00; Y10S148/142; Y10S148/145
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
174 words
A method of fabricating field-effect transistors each having a source, drain and gate electrode comprising the steps of epitaxially growing layers on a semiconductor substrate including at least a current channel followed by a non-alloyed contact to form a semiconductor wafer, depositing a metallic layer over said non-alloyed contact, masking areas on the wafer corresponding to individual field-effect transistors using photoresist material and photolithography techniques, etching the metallic layer and the epitaxially grown layers to develop mesas corresponding to individual field-effect transistors, dissolving the deposited photoresist material used to define the mesa structures, masking the wafer using photolithograhy and photoresist material to define an area in each of the remaining metallic layers at the top of each mesa for the gate electrode structure of each field-effect transistors, etching in the defined areas to remove the exposed metallic layer and the non-alloyed contact, depositing a metallic layer over the entire wafer including the defined areas to form a gate structure in each defined area, and removing the photoresist material deposited during the second masking step.
Claim 2
Independent Claim
174 words
A method of fabricating field-effect transistors each having a source, drain and gate electrode comprising the steps of epitaxially growing layers on a semiconductor substrate including at least a current channel followed by a non-alloyed contact to form a semiconductor wafer, depositing a metallic layer over said non-alloyed contact, masking areas on the wafer corresponding to individual field-effect transistors using photoresist material and photolithography techniques, etching the metallic layer and the epitaxially grown layers to develop mesas corresponding to individual field-effect transistors, dissolving the deposited photoresist material used to define the mesa structures, masking the wafer using photolithograhy and photoresist material to define an area in each of the remaining metallic layers at the top of each mesa for the gate electrode structure of each field-effect transistors, etching in the defined areas to remove the exposed metallic layer and the non-alloyed contact, depositing a metallic layer over the entire wafer including the defined areas to form a gate structure in each defined area, and removing the photoresist material deposited during the second masking step.
Claim 3
Dependent Claim
57 words
A method as defined in claim 1 wherein the step of depositing a metallic layer over said non-alloyed contact comprises the step of depositing a first metal over the non-alloyed contact in order to inhibit the formation of an undesired oxide layer, and depositing a second metal layer consisting of a noble metal over said first metal.
Claim 4
Dependent Claim
51 words
A method as defined in claim 1 wherein the step of depositing a metallic layer so as to form a gate structure comprises the steps of depositing a first metal that adheres well to semiconductor material, and depositing a second metal that consists of a metal having a low ohmic resistance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |