Self-aligned contact for MOS processing

Claim 2

A process of manufacturing a semiconductor device comprising: (a) providing a substrate having a first surface; (b) providing a first dielectric layer over said first surface of said substrate; (c) providing a first conductive layer over said first dielectric layer; (d) providing a second dielectric layer over said first conductive layer; (e) patterning said second dielectric layer, and using said second dielectric layer as a mask for patterning said first conductive layer; (f) patterning said first conductive layer and exposing side surfaces of said first conductive layer; (g) heating said semiconductor device to a predetermined temperature such that said second dielectric layer flows and covers said side surfaces of said first conducting layer, said second dielectric layer forming means for aligning a contact area; (h) removing said first dielectric layer from said contact area; (i) providing a second conductive layer to said contact area.

Claim 3

The process of claim 1, wherein said predetermined temperature is lower than a melting temperature of said first dielectric layer and said first conductive layer.

Claim 4

The process of claim 2, wherein said second dielectric layer includes doped silica glass and said first conductive layer includes a polycrystalline silicon.

Claim 5

The process of claim 3, wherein said substrate is of a first conductivity type, said process further comprising providing active device regions of a second conductivity type in said substrate under said exposed first dielectric layer prior to removing said exposed areas of said first dielectric layer.

Claim 6

The process of claim 4, wherein said doped silica glass includes Borophosphosilicate (BPSG), wherein heating includes heating said BPSG to approximately 900° C., wherein said heating induces said BPSG layer to melt and flow over the exposed side surfaces of said first conductive layer.

Claim 7

The process of claim 5, wherein said substrate includes silicon, and said second conductive layer includes a salicide, said salicide providing interconnecting contacts to said active device regions.

Claim 8

The process of claim 6, wherein said active device regions include source and drain regions and are provided by implanting dopants of said second conductivity type, said process further comprising implanting said dopants a second time after heating said doped silica glass layer, said first implant being of a lighter dosage of dopants relative to said second implant for forming lightly doped drains.

Claim 9

The process of claim 6, further comprising providing an oxide layer on said top surface of said conductive layer before providing said doped silica glass thereon, wherein said composite silica glass and oxide layer are patterned for exposing said selected areas of said conductive layer thereunder, wherein said exposed areas of said conductive layer are then patterned for exposing said first dielectric thereunder.

Claim 10

The process of claim 5, wherein said second conductive layer includes a metal, said metal providing contact points to said respective active regions.

Claim 11

A process for forming an insulated gate field effect semiconductor wafer comprising the steps of: (a) selectively forming a plurality of field oxide regions on a first surface of a substrate such that an active area region is defined between said field oxide regions; (b) providing a thin layer of oxide over the active area region on said first surface of said substrate; (c) providing a conductive layer over said thin layer of oxide; (d) providing a dielectric layer over said conductive layer, wherein said dielectric layer flows when heated to a preselected temperature; (e) selectively removing said first dielectric layer and exposing selected areas of said conductive layer thereunder; (f) selectively removing said exposed regions of said conductive layer and exposing selected areas of said thin oxide layer thereunder, wherein side surfaces of said conductive layer are exposed as a result of said removal of said exposed regions thereof; (g) heating said dielectric layer to said preselected temperature for melting said dielectric layer and covering said exposed side surfaces of said conductive layer; (h) selectively removing said exposed thin oxide and exposing said first surface of said substrate thereunder; and (i) selectively providing a second conductive layer over said exposed portions of said substrate.

Claim 12

A process for forming an insulated gate field effect semiconductor wafer comprising the steps of: (a) selectively forming a plurality of field oxide regions on a first surface of a substrate such that an active area region is defined between said field oxide regions; (b) providing a thin layer of oxide over the active area region on said first surface of said substrate; (c) providing a conductive layer over said thin layer of oxide; (d) providing a dielectric layer over said conductive layer, wherein said dielectric layer flows when heated to a preselected temperature; (e) selectively removing said first dielectric layer and exposing selected areas of said conductive layer thereunder; (f) selectively removing said exposed regions of said conductive layer and exposing selected areas of said thin oxide layer thereunder, wherein side surfaces of said conductive layer are exposed as a result of said removal of said exposed regions thereof; (g) heating said dielectric layer to said preselected temperature for melting said dielectric layer and covering said exposed side surfaces of said conductive layer; (h) selectively removing said exposed thin oxide and exposing said first surface of said substrate thereunder; and (i) selectively providing a second conductive layer over said exposed portions of said substrate.

Claim 13

The process of claim 10, wherein said dielectric layer includes an insulating material having a melting temperature which is lower than a melting temperature of said thin oxide and first conducting layers.

Claim 14

The process of claim 11, wherein said insulating material includes a doped silica glass.

Claim 15

The process of claim 12, wherein said substrate is of first conductivity type, said rocess further comprising the step of providing a source and drain regions of a second conductivity type in said substrate after selectively removing said dielectric layer and said conductive layers.

Claim 16

The process of claim 13, wherein said heating of said dielectric layer includes heating said doped silica glass to approximately 900° C., wherein said heating induces said doped silica glass layer to melt and flow over the exposed surfaces of said conductive layer while also activating said source and drain regions.

Claim 17

The process of claim 14, further comprising the step of providing a second oxide layer on said conductive layer before providing said doped silica glass thereon, wherein said composite silica glass and second oxide layer are patterned and etched for exposing said conductive layer thereunder, wherein said exposed conductive layer is patterned and etched for exposing said thin layer of oxide thereunder.

Claim 18

The process of claim 14, wherein said field oxide regions are selectively formed by a local oxidation and includes a birds beak at an edge of said field oxide regions, said process further comprising the step of providing a masking layer over the edge of said field oxide regions before selectively removing said exposed thin oxide, wherein said masking layer overlaps the junction between said field oxide and said thin layer of oxide for protecting said birds beak of said field oxide during the subsequent removal of said exposed thin oxide.

Claim 19

The process of claim 14, wherein said field oxide regions are selectively formed by providing a layer of oxide covering said top surface of said substrate and patterning said field oxide layer such that said active area region is exposed, wherein said field oxide layer is formed substantially on said top surface of said substrate.

Claim 20

The process of claim 14, wherein said substrate includes silicon and said second conductive layer includes a silicide, said silicide providing respective interconnecting contacts to said source and drain regions.

Claim 21

The process of claim 14, wherein said second conductive layer includes a metal, said metal providing respective interconnecting contacts to said source and drain regions.

Claim 22

The process of claim 14, wherein said source and drain regions are formed by implanting dopants of said second conductivity type using a light dosage, said process further comprising the step of implanting said dopants of said second conductivity type a second time after said heating of said doped silica glass, said second implanting being at a heavier dosage relative to said first implant, wherein lightly doped drain (LDD) regions are formed.

Claim 23

A process for the formation of an insulated gate field effect semiconductor having self-aligned contacts, said process comprising the steps of: (a) providing a substrate having a top surface; (b) selectively forming a gate oxide on selected areas of said top surface of said substrate; (c) selectively forming a first layer of conductive material on said gate oxide, wherein said gate oxide is wider than said first conductive layer such that said gate oxide has an exposed top surface on both sides of said first conductive layer, and said first conductive layer providing the gate for said semiconductor, said gate having exposed top and side surfaces; (d) selectively providing a doped silica glass layer on said exposed top and side surfaces of said gate, such that said glass layer does not completely cover said exposed top surface of said gate oxide; (e) selectively removing said exposed surfaces of said thin gate oxide layer to expose said top surface of said substrate thereunder; and (f) selectively providing a second layer of conductive material on said exposed top surface of said substrate.

Claim 24

A process for the formation of an insulated gate field effect semiconductor having self-aligned contacts, said process comprising the steps of: (a) providing a substrate having a top surface; (b) selectively forming a gate oxide on selected areas of said top surface of said substrate; (c) selectively forming a first layer of conductive material on said gate oxide, wherein said gate oxide is wider than said first conductive layer such that said gate oxide has an exposed top surface on both sides of said first conductive layer, and said first conductive layer providing the gate for said semiconductor, said gate having exposed top and side surfaces; (d) selectively providing a doped silica glass layer on said exposed top and side surfaces of said gate, such that said glass layer does not completely cover said exposed top surface of said gate oxide; (e) selectively removing said exposed surfaces of said thin gate oxide layer to expose said top surface of said substrate thereunder; and (f) selectively providing a second layer of conductive material on said exposed top surface of said substrate.