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US5399514A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing improved lightly doped diffusion (LDD) semiconductor device

Assignee: Seiko Epson Corp
•
Filing: 1993-08-09
•
Granted: 1995-03-21
•
Expires: 2013-08-09
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Abstract

Abstract A semiconductor device comprises at least one p-type and n-type LDD transistors in a pair and a standard (non-LDD) transistor in the same substrate. Appropriate p-wells and n-wells are formed in the substrate, gate electrodes deposited, p-type and n-type first diffusions made, a silicon nitride layer is deposited and removed to leave behind sidewalls on the gates, p-type and n-type second diffusions are made in the LDD transistors, the silicon nitride sidewalls are washed away with a solvent that attacks only the silicon nitride, a third diffusion is made in the standard (non-LDD) transistor(s), a phosphosilicate glass (PSG) layer is applied, contact holes are etched, and an aluminum metalization layer is applied and etched for the interconnect.

Inventors

  • 👤 Matsuo Ichikawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 22:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0147; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8312

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 221 words
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type and a second transistor having a channel of a second conductivity type, the method comprising: forming first and second gates on the substrate for the first and second transistors, respectively; forming a thin insulating layer over the gates and the substrate; forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate; forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second gate in the substrate; concurrently forming sidewalls on the two sides of the first and second gates; forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask; forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask; and concurrently removing the sidewalls on the two sides of the first and second gates so that the first and second transistors are formed as LDD type transistors.
Claim 2
Independent Claim 221 words
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type and a second transistor having a channel of a second conductivity type, the method comprising: forming first and second gates on the substrate for the first and second transistors, respectively; forming a thin insulating layer over the gates and the substrate; forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate; forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second gate in the substrate; concurrently forming sidewalls on the two sides of the first and second gates; forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask; forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask; and concurrently removing the sidewalls on the two sides of the first and second gates so that the first and second transistors are formed as LDD type transistors.
Claim 3
Dependent Claim 143 words
The method of claim 1, wherein: the step of forming a lightly doped region of the first conductivity type includes implanting low concentration impurity ions of the first conductivity type into the substrate on each side of the first gate; the step of forming a lightly doped region of the second conductivity type includes implanting low concentration impurity ions of the second conductivity type into the substrate on each side of the second gate; the step of forming a heavily doped region of the first conductivity type includes implanting high concentration impurity ions of the first conductivity type into the substrate on each side of the first gate; and the step of forming a heavily doped region of the second conductivity type includes implanting high concentration impurity ions of the second conductivity type into the substrate on each side of the second gate.
Claim 4
Dependent Claim 110 words
The method of claim 2, wherein: forming sidewalls comprises forming silicon nitride sidewalls; implanting low concentration impurity ions of the first conductivity type includes implanting low concentration impurity ions of p-type conductivity; implanting low concentration impurity ions of the second conductivity type includes implanting low concentration impurity ions of n-type conductivity; implanting high concentration impurity ions of the first conductivity type includes implanting high concentration impurity ions of p-type conductivity; implanting high concentration impurity ions of the second conductivity type includes implanting high concentration impurity ions of n-type conductivity; the first transistor is formed as a p-channel MOS transistor; and the second transistor is formed as an n-channel MOS transistor.
Claim 5
Dependent Claim 32 words
The method of claim 2 wherein the step of forming sidewalls comprises forming a silicon nitride layer on the thin insulating layer and etching the silicon nitride layer to form the sidewalls.
Claim 6
Dependent Claim 31 words
The method of claim 2 wherein the step of forming sidewalls comprises forming a polycrystalline silicon layer on the thin insulating layer and etching the silicon layer to form the sidewalls.
Claim 7
Dependent Claim 110 words
The method of claim 2 wherein forming sidewalls comprises forming polycrystalline silicon sidewalls; implanting low concentration impurity ions of the first conductivity type includes implanting low concentration impurity ions of p-type conductivity; implanting low concentration impurity ions of the second conductivity type includes implanting low concentration impurity ions of n-type conductivity; implanting high concentration impurity ions of the first conductivity type includes implanting high concentration impurity ions of p-type conductivity; implanting high concentration impurity ions of the second conductivity type includes implanting high concentration impurity ions of n-type conductivity; the first transistor is formed as a p-channel MOS transistor; and the second transistor is formed as an n-channel MOS transistor.
Claim 8
Dependent Claim 42 words
The method of claim 6 further comprising: forming a phosphosilicate glass layer on the thin insulating layer; and creating contact holes in the glass layer and the thin insulating layer to expose the substrate at the sources and drains of the transistors.
Claim 9
Independent Claim 261 words
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type, and second and third transistors each having a channel of a second conductivity type, the method comprising: forming first, second and third gates on the substrate for the first, second and third transistors, respectively; forming a thin insulating layer over the gates and the substrate; forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate; forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second and third gates in the substrate; concurrently forming sidewalls on the two sides of the first, second and third gates; forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask; forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask; concurrently removing the sidewalls on the two sides of the first, second and third gates so that the first and second transistors are formed as LDD type transistors; and forming a heavily doped region of the second conductivity type on each side of the third gate in the substrate so that the third transistor is formed as a non-LDD type transistor.
Claim 10
Independent Claim 261 words
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type, and second and third transistors each having a channel of a second conductivity type, the method comprising: forming first, second and third gates on the substrate for the first, second and third transistors, respectively; forming a thin insulating layer over the gates and the substrate; forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate; forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second and third gates in the substrate; concurrently forming sidewalls on the two sides of the first, second and third gates; forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask; forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask; concurrently removing the sidewalls on the two sides of the first, second and third gates so that the first and second transistors are formed as LDD type transistors; and forming a heavily doped region of the second conductivity type on each side of the third gate in the substrate so that the third transistor is formed as a non-LDD type transistor.
Claim 11
Dependent Claim 193 words
The method of claim 8, wherein: the step of forming a lightly doped region of the first conductivity type includes implanting low concentration impurity ions of the first conductivity type into the substrate on each side of the first gate; the step of forming a lightly doped region of the second conductivity type includes implanting low concentration impurity ions of the second conductivity type into the substrate on each side of the second and third gates; the step of forming a heavily doped region of the first conductivity type includes implanting high concentration impurity ions of the first conductivity type into the substrate on each side of the first gate; the step of forming a heavily doped region of the second conductivity type underneath each side of the second gate includes implanting high concentration impurity ions of the second conductivity type into the substrate on each side of the second gate; and the step of forming a heavily doped region of the second conductivity type underneath each side of the third gate includes implanting high concentration impurity ions of the second conductivity type into the substrate on each side of the third gate.
Claim 12
Dependent Claim 110 words
The method of claim 9, wherein: forming sidewalls comprises forming silicon nitride sidewalls; implanting low concentration impurity ions of the first conductivity type includes implanting low concentration impurity ions of p-type conductivity; implanting low concentration impurity ions of the second conductivity type includes implanting low concentration impurity ions of n-type conductivity; implanting high concentration impurity ions of the first conductivity type includes implanting high concentration impurity ions of p-type conductivity; implanting high concentration impurity ions of the second conductivity type includes implanting high concentration impurity ions of n-type conductivity; the first transistor is formed as a p-channel MOS transistor; and the second transistor is formed as an n-channel MOS transistor.
Claim 13
Dependent Claim 110 words
The method of claim 9 wherein forming sidewalls comprises forming polycrystalline silicon sidewalls; implanting low concentration impurity ions of the first conductivity type includes implanting low concentration impurity ions of p-type conductivity; implanting low concentration impurity ions of the second conductivity type includes implanting low concentration impurity ions of n-type conductivity; implanting high concentration impurity ions of the first conductivity type includes implanting high concentration impurity ions of p-type conductivity; implanting high concentration impurity ions of the second conductivity type includes implanting high concentration impurity ions of n-type conductivity; the first transistor is formed as a p-channel MOS transistor; and the second transistor is formed as an n-channel MOS transistor.
Claim 14
Dependent Claim 42 words
The method of claim 11 further comprising: forming a phosphosilicate glass layer over the thin insulating layer; and creating contact holes in the glass layer and the thin insulating layer to expose the substrate at the sources and drains of the transistors.
Claim 15
Dependent Claim 32 words
The method of claim 9 wherein the step of forming sidewalls comprises forming a silicon nitride layer on the thin insulating layer and etching the silicon nitride layer to form the sidewalls.
Claim 16
Dependent Claim 31 words
The method of claim 9 wherein the step of forming sidewalls comprises forming a polycrystalline silicon layer on the thin insulating layer and etching the silicon layer to form the sidewalls.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-03-20 1998-09-19 1999-03-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-03-20 2002-09-19 2003-03-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-03-20 2006-09-19 2007-03-21 $7700.00 Window Closed / Lapsed

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