Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions

Claim 2

A process of fabricating an integrated circuit on a semiconductor substrate, the integrated circuit having at least one pin and at least one power rail, the process comprising the steps of: fabricating lightly doped drain (LDD) devices arranged in a pattern on a substrate of a first conductivity type; coupling said LDD devices to a pin of the integrated circuit; and fabricating a non-LDD metal oxide semiconductor (MOS) device on said substrate, said non-LDD MOS device being coupled between said pin and a power rail of the integrated circuit, said non-LDD MOS device having a highly-doped source region, a highly-doped drain region and a gate region, each of said highly-doped source and drain regions being separated from said gate region by an undoped region, wherein in the event of an ESD occurrence at the pin, a portion of the ESD is dissipated through the non-LDD MOS device to said power rail.

Claim 3

The process of claim 1, wherein the step of fabricating one of said non-LDD MOS devices on the integrated circuit (IC) comprises the steps of: forming a gate oxide and a gate on the substrate, said gate oxide and said gate defining sidewalls on said substrate; forming said highly doped source and drain regions of a second conductivity type in said substrate a predetermined lateral distance from said sidewalls; coupling a first of said highly doped source and drain regions to the pin of the IC; and coupling a second of said highly doped source and drain regions to the rail of the IC, wherein, in the occurrence of an ESD event at the pin, said first highly doped region, said channel region, and said second highly doped region form a conductive path to dissipate the ESD between the pin and the rail, thereby protecting said other LDD devices on the integrated circuit.

Claim 4

The process of claim 2, wherein said step of forming said highly doped source and drain regions comprises the steps of: forming a spacer oxide of said predteremined thickness around said sidewalls of said gate on the substrate; using said spacer oxide as a mask, introducing impurities of a second type into said substrate so that said highly doped source and drain regions are formed said predetermined lateral distance from said sidewalls in said substrate.

Claim 5

The process of claim 1, wherein said steps of fabricating said LDD and non-LDD devices occur substantially concurrent with one another.

Claim 6

A MOS process flow for forming a lightly doped drain (LDD) MOS device of a first conductivity type, and non-LDD MOS device of the first conductivity type, comprising the steps of: forming a first gate oxide and first gate on a first portion of a substrate of a second conductivity type; forming a second gate oxide and second gate on a second portion of said substrate; forming first lightly doped source and drain regions of said first conductivity type adjacent said first gate oxide and first gate in said first portion of said substrate; forming second lightly doped source and drain regions of said first conductivity type a predetermined lateral distance from said second gate oxide and said second gate in said second portion of said substrate such that each of said second lightly doped source and drain regions is separated from said gate region by an undoped region; forming a first spacer oxide around said first gate oxide and first gate, said first spacer oxide having a lateral dimension substantially equal to said predetermined lateral dimension; forming a second spacer oxide around said second gate oxide and second gate, said second spacer oxide having a lateral dimension substantially equal to said predetermined lateral dimension; using said first spacer oxide as a mask, forming highly doped regions of said first conductivity type within said first lightly doped source and drain regions, thus forming a LDD MOS device; and using said second spacer oxide as a mask, forming highly doped regions of said first conductivity type within said second lightly doped source and drain regions such that each of said highly-doped regions is separated from said gate region by said undoped region, thus forming an non-LDD MOS device.

Claim 7

A MOS process flow for forming a lightly doped drain (LDD) MOS device of a first conductivity type, and non-LDD MOS device of the first conductivity type, comprising the steps of: forming a first gate oxide and first gate on a first portion of a substrate of a second conductivity type; forming a second gate oxide and second gate on a second portion of said substrate; forming first lightly doped source and drain regions of said first conductivity type adjacent said first gate oxide and first gate in said first portion of said substrate; forming second lightly doped source and drain regions of said first conductivity type a predetermined lateral distance from said second gate oxide and said second gate in said second portion of said substrate such that each of said second lightly doped source and drain regions is separated from said gate region by an undoped region; forming a first spacer oxide around said first gate oxide and first gate, said first spacer oxide having a lateral dimension substantially equal to said predetermined lateral dimension; forming a second spacer oxide around said second gate oxide and second gate, said second spacer oxide having a lateral dimension substantially equal to said predetermined lateral dimension; using said first spacer oxide as a mask, forming highly doped regions of said first conductivity type within said first lightly doped source and drain regions, thus forming a LDD MOS device; and using said second spacer oxide as a mask, forming highly doped regions of said first conductivity type within said second lightly doped source and drain regions such that each of said highly-doped regions is separated from said gate region by said undoped region, thus forming an non-LDD MOS device.

Claim 8

The MOS process flow of claim 5, further comprising the step of forming a complementary MOS device having a channel of a second conductivity type within a well of said first conductivity type formed in said substrate of said second conductivity type.

Claim 9

The MOS process flow of claim 5, wherein said predetermined lateral dimension is 0.2 microns.

Claim 10

The MOS process flow of claim 5, wherein said second conductivity type is N type.

Claim 11

The MOS process flow of claim 5, wherein said second conductivity type is P type.