Substrate bias generating circuit

Claim 2

A substrate bias generating circuit for providing a substrate bias voltage, comprising: a voltage-to-current converter circuit having an input terminal for receiving a bandgap generated reference voltage, and in response, generating a reference current proportional to said bandgap generated reference voltage; a first current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal, said first current source for providing a first current proportional to said reference current; a second current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, said second current source for providing a second current proportional to said reference current; a voltage level sensing circuit, comprising: a first resistor having a first terminal coupled to said second terminal of said first current source, and a second terminal; a second resistor having a first terminal coupled to said second terminal of said first resistor, and a second terminal; a first N-channel transistor having a first current electrode coupled to said second terminal of said second current source, a control electrode coupled to said second terminal of said first resistor, and a second current electrode coupled to a second power supply voltage terminal; and a second N-channel transistor having a first current electrode coupled to said second terminal of said second resistor, a control electrode coupled to said second terminal of said second resistor, and a second current electrode for receiving said substrate bias voltage said second N-channel transistor for compensating for temperature and process variations of said first N-channel transistor; an oscillator having an input terminal coupled to said voltage level sensing circuit, and an output terminal for producing a series of pulses at a predetermined frequency; and a charge pump having an input terminal coupled said output terminal of said oscillator, for receiving said series of pulses, and for providing said substrate bias voltage.

Claim 3

The substrate bias generating circuit of claim 1, wherein said voltage-to-current converter circuit comprises: a differential amplifier having first and second bipolar transistors and a current mirror, a base of said first bipolar transistor for receiving said bandgap generated reference voltage; a first P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to a collector of said first bipolar transistor, and a second current electrode; and a third resistor having a first terminal coupled to said second current electrode of said first P-channel transistor, and a second terminal coupled to said second power supply voltage terminal.

Claim 4

The substrate bias generating circuit of claim 2, further comprising a level converter circuit, said level converter circuit comprising: a second P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode; and a third N-channel transistor having a first current electrode coupled to said second current electrode of said second P-channel transistor, a control electrode coupled to said second terminal of said second current source, and a second current electrode coupled to said second power supply voltage terminal.

Claim 5

The substrate bias generating circuit of claim 1, wherein said first and second current sources are characterized as being P-channel transistors.

Claim 6

The substrate bias generating circuit of claim 1, wherein said first power supply voltage terminal is for receiving a first power supply voltage and said second power supply voltage terminal is for receiving a second power supply voltage, said substrate bias voltage is provided at a predetermined voltage level below said second power supply voltage.

Claim 7

The substrate bias generating circuit of claim 1, wherein said oscillator is a ring oscillator.

Claim 8

A substrate bias generating circuit, comprising: a voltage-to-current converter, comprising: a differential amplifier having first and second bipolar transistors and a current mirror, a collector of each of the first and second bipolar transistors coupled to the current mirror, and emitters of the first and second bipolar transistors coupled together, a base of said first bipolar transistor for receiving a bandgap generated reference voltage; a first P-channel transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to a collector of said first bipolar transistor, and a second current electrode coupled to a base of the second bipolar transistor, said first P-channel transistor providing a first current; and a first resistor having a first terminal coupled to said second current electrode of said first P-channel transistor, and a second terminal coupled to a second power supply voltage terminal; a second P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode, said second P-channel transistor providing a second current; a third P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode; a voltage level sensing circuit, comprising: a second resistor having a first terminal coupled to said second current electrode of said second P-channel transistor, and a second terminal; a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, a first voltage drop across said third resistor is directly proportional to a second voltage drop across said first resistor for compensating for temperature and process variations of said first resistor; and a first N-channel transistor having a first current electrode coupled to said second current electrode of said third P-channel transistor, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to a second power supply voltage terminal; a second N-channel transistor having a first current electrode coupled to said second terminal of said third resistor, a control electrode coupled to said second terminal of said third resistor, and a second current electrode for receiving a substrate bias voltage, said second N-channel transistor for compensating for temperature and process variations of said first N-channel transistor; an oscillator having an input terminal coupled to said first current electrode of said first N-channel transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency; and a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.

Claim 9

A substrate bias generating circuit, comprising: a voltage-to-current converter, comprising: a differential amplifier having first and second bipolar transistors and a current mirror, a collector of each of the first and second bipolar transistors coupled to the current mirror, and emitters of the first and second bipolar transistors coupled together, a base of said first bipolar transistor for receiving a bandgap generated reference voltage; a first P-channel transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to a collector of said first bipolar transistor, and a second current electrode coupled to a base of the second bipolar transistor, said first P-channel transistor providing a first current; and a first resistor having a first terminal coupled to said second current electrode of said first P-channel transistor, and a second terminal coupled to a second power supply voltage terminal; a second P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode, said second P-channel transistor providing a second current; a third P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode; a voltage level sensing circuit, comprising: a second resistor having a first terminal coupled to said second current electrode of said second P-channel transistor, and a second terminal; a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, a first voltage drop across said third resistor is directly proportional to a second voltage drop across said first resistor for compensating for temperature and process variations of said first resistor; and a first N-channel transistor having a first current electrode coupled to said second current electrode of said third P-channel transistor, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to a second power supply voltage terminal; a second N-channel transistor having a first current electrode coupled to said second terminal of said third resistor, a control electrode coupled to said second terminal of said third resistor, and a second current electrode for receiving a substrate bias voltage, said second N-channel transistor for compensating for temperature and process variations of said first N-channel transistor; an oscillator having an input terminal coupled to said first current electrode of said first N-channel transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency; and a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.

Claim 10

The substrate bias generating circuit of claim 7, wherein said oscillator is a ring oscillator.

Claim 11

The substrate bias generating circuit of claim 7, wherein said first power supply voltage terminal is for receiving a first power supply voltage and said second power supply voltage terminal is for receiving a second power supply voltage, said substrate bias voltage is provided at a predetermined voltage level below said second power supply voltage.

Claim 12

The substrate bias generator of claim 7, further comprising a level converter circuit, said level converter circuit comprising: a fourth P-channel transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said control electrode of said first P-channel transistor, and a second current electrode; and a third N-channel transistor having a first current electrode coupled to said second current electrode of said fourth P-channel transistor, a control electrode coupled to said second current electrode of said third P-channel transistor, and a second current electrode coupled to said second power supply voltage terminal.

Claim 13

A substrate bias generating circuit for providing a substrate bias voltage, comprising: a differential amplifier having a first input terminal for receiving a reference voltage, a second input terminal, and an output terminal; a first current source having a first terminal coupled to a first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal coupled to said second input terminal of said differential amplifier, said first current source for providing a first current; a second current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a second current; a first resistor having a first terminal coupled to said second terminal of said first current source for receiving said first current, and a second terminal coupled to a second power supply voltage terminal; a second resistor having a first terminal coupled to said second terminal of said second current source, and a second terminal; a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, said third resistor for receiving said second current, and compensating for temperature and process variations of said first resistor; a first MOS transistor having a first current electrode and a control electrode both coupled to said second terminal of said third resistor, and a second current electrode for receiving said substrate bias voltage; a third current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a third current; a second MOS transistor having a first current electrode coupled to said second terminal of said third current source, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to said second power supply voltage terminal, said second MOS transistor for compensating for temperature and process variations of said first MOS transistor; an oscillator having an input terminal coupled to said first current electrode of said fourth MOS transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency; and a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.

Claim 14

A substrate bias generating circuit for providing a substrate bias voltage, comprising: a differential amplifier having a first input terminal for receiving a reference voltage, a second input terminal, and an output terminal; a first current source having a first terminal coupled to a first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal coupled to said second input terminal of said differential amplifier, said first current source for providing a first current; a second current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a second current; a first resistor having a first terminal coupled to said second terminal of said first current source for receiving said first current, and a second terminal coupled to a second power supply voltage terminal; a second resistor having a first terminal coupled to said second terminal of said second current source, and a second terminal; a third resistor having a first terminal coupled to said second terminal of said second resistor, and a second terminal, said third resistor for receiving said second current, and compensating for temperature and process variations of said first resistor; a first MOS transistor having a first current electrode and a control electrode both coupled to said second terminal of said third resistor, and a second current electrode for receiving said substrate bias voltage; a third current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal for providing a third current; a second MOS transistor having a first current electrode coupled to said second terminal of said third current source, a control electrode coupled to said second terminal of said second resistor, and a second current electrode coupled to said second power supply voltage terminal, said second MOS transistor for compensating for temperature and process variations of said first MOS transistor; an oscillator having an input terminal coupled to said first current electrode of said fourth MOS transistor, and an output terminal, said oscillator for producing a series of pulses at a predetermined frequency; and a charge pump having an input terminal coupled to said output terminal of said oscillator for receiving said series of pulses, and an output terminal for providing said substrate bias voltage.

Claim 15

The substrate bias generating circuit of claim 11, wherein said reference voltage is a bandgap generated reference voltage.

Claim 16

The substrate bias generating circuit of claim 11, wherein said first, second, and third current sources are P-channel transistors.

Claim 17

The substrate bias generating circuit of claim 11, wherein said differential amplifier comprises: a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate, and a drain; a second P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain; a first NPN transistor having a collector coupled to said drain of said first P-channel transistor, a base for receiving said reference voltage, and an emitter; and a second NPN transistor having a collector coupled to said drain of said second P-channel transistor, a base coupled to said second terminal of said first current source, and an emitter coupled to said emitter of said first bipolar transistor.

Claim 18

The substrate bias generating circuit of claim 11, further comprising: a fourth current source having a first terminal coupled to said first power supply voltage terminal, a control terminal coupled to said output terminal of said differential amplifier, and a second terminal; and a third MOS transistor having a first current electrode coupled to said second terminal of said fourth current source, a control electrode coupled to said first current electrode of said second MOS transistor, and a second current electrode coupled to said second power supply voltage terminal.