Voltage detecting circuit

Claim 2

A voltage detecting circuit comprising first and second lines connected respectively to terminals of a voltage source of which a predetermined drop in voltage is to be detected, a voltage divider and a first MOS transistor having a gate connected in series with one another between said lines, said voltage divider comprising first and second resistance means connected in series with one another with an intermediate tap between them, first inverter means comprising a second MOS transistor having a gate and third resistance means connected in series with one another between said first and second lines with an output between said second MOS transistor and said third resistance means, means connecting the gate of said second MOS transistor with said tap, second inverter means comprising an N-MOS transistor and a P-MOS transistor each having a gate connected in series with one another between said first and second lines with an output providing a voltage indicating signal between said N-MOS transistor and said P-MOS transistor, means connecting the output of said first inverter means with the gates of said N-MOS transistor and said P-MOS transistor and means for periodically applying a signal pulse to the gate of said first MOS transistor, the ratio of current to the conductive constant of said MOS transistor being above 0.1 whereby said predetermined drop in voltage is determined by the dividing ratio of said voltage divider with compensation for temperature variation.

Claim 3

A voltage detecting circuit according to claim 1, comprising at least one additional MOS transistor connected in series with a resistance between said second line and said tap, said additional MOS transistor having a gate and means for selectively applying said pulse to said gate of said additional transistor.

Claim 4

A voltage detection circuit comprising: a logic circuit including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type being opposite to said first conductivity type, wherein the gate electrodes of said first and second MISFETs are commonly connected, the drain electrodes of said first and said second MISFETs are commonly connected to a detection output electrode, and the source electrodes of said first and said second MISFETs are respectively connected to first and second prescribed potentials; A voltage dividing circuit for applying a divided voltage of a potential difference between said first and said second prescribed potentials to said gate electrodes of said first and said second MISFETs in said logic circuit, including a third MISFET of said second conductivity type and a load resistive element, wherein the source electrode of said third MISFET is connected to said second prescribed potential and the drain electrode of said third MISFET is connected to said first prescribed potential through said load resistive element and is coupled with said gate electrodes of said first and said second MISFETs; and a bias circuit for applying a bias voltage to the gate electrode of said third MISFET, including first and second linear resistors connected in series between said first and said second prescribed potentials, wherein the juncture of said first and said second linear resistors is connected to the gate electrode of said third MISFET, thus compensating for temperature variations in threshold voltages of said first, second and third MISFETs, in which said bias circuit further includes a fourth MISFET connected in series with said second linear resistor and means for periodically applying a signal pulse to the gate of said fourth MISFET.

Claim 5

A voltage detection circuit comprising: a logic circuit including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type being opposite to said first conductivity type, wherein the gate electrodes of said first and second MISFETs are commonly connected, the drain electrodes of said first and said second MISFETs are commonly connected to a detection output electrode, and the source electrodes of said first and said second MISFETs are respectively connected to first and second prescribed potentials; A voltage dividing circuit for applying a divided voltage of a potential difference between said first and said second prescribed potentials to said gate electrodes of said first and said second MISFETs in said logic circuit, including a third MISFET of said second conductivity type and a load resistive element, wherein the source electrode of said third MISFET is connected to said second prescribed potential and the drain electrode of said third MISFET is connected to said first prescribed potential through said load resistive element and is coupled with said gate electrodes of said first and said second MISFETs; and a bias circuit for applying a bias voltage to the gate electrode of said third MISFET, including first and second linear resistors connected in series between said first and said second prescribed potentials, wherein the juncture of said first and said second linear resistors is connected to the gate electrode of said third MISFET, thus compensating for temperature variations in threshold voltages of said first, second and third MISFETs, in which said bias circuit further includes a fourth MISFET connected in series with said second linear resistor and means for periodically applying a signal pulse to the gate of said fourth MISFET.