Patent US5389834A successfully refreshed from Google Patents.
US5389834A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer circuit having a DC driver and an AC driver
Assignee: Toshiba Corp
•
Filing: 1992-11-12
•
Granted: 1995-02-14
•
Expires: 2012-11-12
Abstract
Abstract This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.
Inventors
- 👤 Masanori Kinugasa
- 👤 Satoshi Nonaka
- 👤 Hiroshi Shigehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
268 words
An output buffer circuit comprising: an output terminal; a first output buffer having an output node connected to said output terminal, and an output resistance determined from DC specifications; a second output buffer having an output node connected to said output terminal, and an output resistance determined from AC specifications when said second output buffer is driven with said first output buffer; first control means having a first enable input line and a first data input line for controlling an operation of said first output buffer, said first control means driving said first output buffer according to a logic level of said first data input line when said first enable input line has a first logic level, and said first control means setting said first output buffer in a high-impedance state when said first enable input line has a second logic level opposite of said first logic level of said first enable input line; and second control means having a second enable input line for controlling an operation of a second output buffer, said second control means driving said second output buffer when an output at said output node of said first output buffer changes and when said second enable input line has a first logic level, said second control means maintaining said second output buffer in a high-impedance state when said second enable input line has a second logic level opposite of said first logic level of said second enable input line, and said second control means connecting said output node of said first output buffer to said second output buffer only through current paths of transistors.
Claim 2
Dependent Claim
268 words
An output buffer circuit comprising: an output terminal; a first output buffer having an output node connected to said output terminal, and an output resistance determined from DC specifications; a second output buffer having an output node connected to said output terminal, and an output resistance determined from AC specifications when said second output buffer is driven with said first output buffer; first control means having a first enable input line and a first data input line for controlling an operation of said first output buffer, said first control means driving said first output buffer according to a logic level of said first data input line when said first enable input line has a first logic level, and said first control means setting said first output buffer in a high-impedance state when said first enable input line has a second logic level opposite of said first logic level of said first enable input line; and second control means having a second enable input line for controlling an operation of a second output buffer, said second control means driving said second output buffer when an output at said output node of said first output buffer changes and when said second enable input line has a first logic level, said second control means maintaining said second output buffer in a high-impedance state when said second enable input line has a second logic level opposite of said first logic level of said second enable input line, and said second control means connecting said output node of said first output buffer to said second output buffer only through current paths of transistors.
Claim 3
Dependent Claim
15 words
A circuit according to claim 1, wherein said second output buffer comprises a MOS transistor.
Claim 4
Dependent Claim
149 words
A circuit according to claim 1, wherein said second output buffer comprises a p-channel MOS current-source transistor connected between a high-potential power supply and said output node of said first output buffer, and said second control means sets said current-source transistor in an ON state when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-source transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means connects said control electrode of said current-source transistor to said high-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 5
Dependent Claim
149 words
A circuit according to claim 1, wherein said second output buffer comprises an n-channel MOS current-sink transistor connected between said output node of said first output buffer and a low-potential power supply, and said second control means sets said current-sink transistor in an ON state when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-sink transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means connects said control electrode of said current-sink transistor to said low-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 6
Dependent Claim
194 words
A circuit according to claim 1, wherein said second output buffer comprises a p-channel MOS current-source transistor connected between a high-potential power supply and said output node of said first output buffer and an n-channel MOS current-sink transistor connected between said output node of said first output buffer and a low-potential power supply, and wherein said second control means sets said current-source transistor in an ON state and connects a control electrode of said current-sink transistor to said low-potential power supply when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-source transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means sets said current-sink transistor in an ON state and connects said control electrode of said current-source transistor to said high-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 7
Dependent Claim
35 words
A circuit according to claim 3, wherein said second control means connects said control electrode of said current-source transistor to said low-potential power supply in order to set said current-source transistor in said ON state.
Claim 8
Dependent Claim
39 words
A circuit according to claim 3, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer in order to set said current-source transistor in said ON state.
Claim 9
Dependent Claim
51 words
A circuit according to claim 3, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 10
Dependent Claim
99 words
A circuit according to claim 5, wherein said second control means has a first switching element connected between said high-potential power supply and said control electrode of said current-source transistor, a second switching element connected between said control electrode of said current-source transistor and said output node of said first output buffer, and a third switching element connected between said control electrode of said current-source transistor and one of said low potential power supply and said output node of said first output buffer, and said first, second, and third switching elements are controlled in accordance with a predetermined sequence.
Claim 11
Dependent Claim
35 words
A circuit according to claim 4, wherein said second control means connects said control electrode of said current-sink transistor to said high-potential power supply in order to set said current-sink transistor in said ON state.
Claim 12
Dependent Claim
39 words
A circuit according to claim 4, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer in order to set said current-sink transistor in said ON state.
Claim 13
Dependent Claim
51 words
A circuit according to claim 4, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 14
Dependent Claim
82 words
A circuit according to claim 9, wherein said second control means has a fourth switching element connected between said control electrode of said current-sink transistor and said low-potential power supply, a fifth switching element connected between said control electrode of said current-sink transistor and said output node of said first output buffer, and a sixth switching element connected between said control electrode of said current-sink transistor and one of said high-potential power supply and said output node of said first output buffer.
Claim 15
Dependent Claim
35 words
A circuit according to claim 5, wherein said second control means connects said control electrode of said current-source transistor to said low-potential power supply in order to set said current-source transistor in said ON state.
Claim 16
Dependent Claim
39 words
A circuit according to claim 5, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer in order to set said current-source transistor in said ON state.
Claim 17
Dependent Claim
51 words
A circuit according to claim 5, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 18
Dependent Claim
35 words
A circuit according to claim 5, wherein said second control means connects said control electrode of said current-sink transistor to said high-potential power supply in order to set said current-sink transistor in said ON state.
Claim 19
Dependent Claim
39 words
A circuit according to claim 5, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer in order to set said current-sink transistor in said ON state.
Claim 20
Dependent Claim
15 words
A circuit according to claim 1, wherein said second output buffer comprises a bipolar transistor.
Claim 21
Dependent Claim
148 words
A circuit according to claim 1, wherein said second output buffer comprises a pnp current-source transistor connected between a high-potential power supply and said output node of said first output buffer, and said second control means sets said current-source transistor in an ON state when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-source transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means connects said control electrode of said current-source transistor to said high-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 22
Dependent Claim
148 words
A circuit according to claim 1, wherein said second output buffer comprises an npn current-sink transistor connected between said output node of said first output buffer and a low-potential power supply, and said second control means sets said current-sink transistor in an ON state when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-sink transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means connects said control electrode of said current-sink transistor to said low-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 23
Dependent Claim
192 words
A circuit according to claim 1, wherein said second output buffer comprises a pnp current-source transistor connected between a high-potential power supply and said output node of said first output buffer and an npn current-sink transistor connected between said output node of said first output buffer and a low-potential power supply, and wherein said second control means sets said current-source transistor in an ON state and connects a control electrode of said current-sink transistor to said low-potential power supply when said output at said output node of said first output buffer changes from a first logic level to a second logic level, said second control means connects a control electrode of said current-source transistor to said output node of said first output buffer when said output at said output node of said first output buffer is stationary at said second logic level, and said second control means sets said current-sink transistor in an ON state and connects said control electrode of said current-source transistor to said high-potential power supply when said output at said output node of said first output buffer changes from said second logic level to said first logic level.
Claim 24
Dependent Claim
35 words
A circuit according to claim 20, wherein said second control means connects said control electrode of said current-source transistor to said low-potential power supply in order to set said current-source transistor in said ON state.
Claim 25
Dependent Claim
39 words
A circuit according to claim 20, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer in order to set said current-source transistor in said ON state.
Claim 26
Dependent Claim
51 words
A circuit according to claim 20, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 27
Dependent Claim
99 words
A circuit according to claim 22, wherein said second control means has a first switching element connected between said high-potential power supply and said control electrode of said current-source transistor, a second switching element connected between said control electrode of said current-source transistor and said output node of said first output buffer, and a third switching element connected between said control electrode of said current-source transistor and one of said low potential power supply and said output node of said first output buffer, and said first, second, and third switching elements are controlled in accordance with a predetermined sequence.
Claim 28
Dependent Claim
35 words
A circuit according to claim 21, wherein said second control means connects said control electrode of said current-sink transistor to said high-potential power supply in order to set said current-sink transistor in said ON state.
Claim 29
Dependent Claim
39 words
A circuit according to claim 21, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer in order to set said current-sink transistor in said ON state.
Claim 30
Dependent Claim
51 words
A circuit according to claim 21, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 31
Dependent Claim
82 words
A circuit according to claim 26, wherein said second control means has a fourth switching element connected between said control electrode of said current-sink transistor and said low-potential power supply, a fifth switching element connected between said control electrode of said current-sink transistor and said output node of said first output buffer, and a sixth switching element connected between said control electrode of said current-sink transistor and one of said high-potential power supply and said output node of said first output buffer.
Claim 32
Dependent Claim
35 words
A circuit according to claim 22, wherein said second control means connects said control electrode of said current-source transistor to said low-potential power supply in order to set said current-source transistor in said ON state.
Claim 33
Dependent Claim
39 words
A circuit according to claim 22, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer in order to set said current-source transistor in said ON state.
Claim 34
Dependent Claim
51 words
A circuit according to claim 22, wherein said second control means connects said control electrode of said current-source transistor to said output node of said first output buffer through a diode element when said output at said output node of said first output buffer is stationary at said second logic level.
Claim 35
Dependent Claim
35 words
A circuit according to claim 22, wherein said second control means connects said control electrode of said current-sink transistor to said high-potential power supply in order to set said current-sink transistor in said ON state.
Claim 36
Dependent Claim
39 words
A circuit according to claim 22, wherein said second control means connects said control electrode of said current-sink transistor to said output node of said first output buffer in order to set said current-sink transistor in said ON state.
References Cited (Backward Citations)
US4678943A
Cited
US4612466A
Cited
US4731553A
Cited
US4829199A
Cited
US4928023A
Cited
US5047669A
Cited
US5059821A
Cited
US5132568A
Cited
US5212801A
Cited
US5107142A
Cited
US5220205A
Cited
EP0511643A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |