US5132568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tri-state output circuit utilizing a BiCMOS inverter circuit
Assignee: KOREA TELECOMMUNICATIONS AUTHORITY A CORP OF KOREA
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Filing: 1991-04-22
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Granted: 1992-07-21
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Expires: 2011-04-22
Abstract
Abstract A tri-state logic circuit of a BiCMOS having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching charaacteristic is disclosed. The circuit comprises PMOS transistors M1,M5 and NMOS transistors M2,M3,M4,M6,M7,M8,M9 and bipolar transistors Q1,Q2 and a capacitor C1.
Inventors
- 👤 Young M. Kim
- 👤 Won C. Song
- 👤 Jin I. Hyun
- 👤 Hah Y. Yoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/0008; H03K19/001
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
269 words
A tri-state output circuit utilizing a BiCMOS inverter circuit comprising: an input node (Data in) connected to the gate electrode of a first PMOS transistor and a first and a second NMOS transistors; a second PMOS transistor and a third and a fourth NMOS transistors with a tri-state control signal applied to each gate electrode thereof; the second PMOS transistor having a source electrode connected to a driving voltage source, and a drain electrode connected to a drain electrode of the third NMOS transistor and to a source electrode of the first PMOS transistor; the first NMOS transistor having a source electrode connected to a ground, and a drain electrode connected to the drain electrode of the first PMOS transistor; the first PMOS transistor having a drain electrode connected to a base electrode of a first NPN bipolar transistor and to the drain electrode of the fourth NMOS transistor, the source electrode of which is connected to a ground; the first NPN transistor having a collector electrode connected to the driving voltage source, and an emitter electrode connected to an output node (Data out), and to a capacitor and the collector electrode of a second NPN bipolar transistor, and to the drain electrode of the second NMOS transistor; a fifth NMOS transistor having a drain electrode connected to the source electrode of the second NMOS transistor, and a source electrode connected to the base electrode of the second NPN bipolar transistor, the emitter of which is connected to a ground; and a sixth and a seventh NMOS transistors connected to the base electrode of the second NPN bipolar transistor.
Claim 2
Dependent Claim
269 words
A tri-state output circuit utilizing a BiCMOS inverter circuit comprising: an input node (Data in) connected to the gate electrode of a first PMOS transistor and a first and a second NMOS transistors; a second PMOS transistor and a third and a fourth NMOS transistors with a tri-state control signal applied to each gate electrode thereof; the second PMOS transistor having a source electrode connected to a driving voltage source, and a drain electrode connected to a drain electrode of the third NMOS transistor and to a source electrode of the first PMOS transistor; the first NMOS transistor having a source electrode connected to a ground, and a drain electrode connected to the drain electrode of the first PMOS transistor; the first PMOS transistor having a drain electrode connected to a base electrode of a first NPN bipolar transistor and to the drain electrode of the fourth NMOS transistor, the source electrode of which is connected to a ground; the first NPN transistor having a collector electrode connected to the driving voltage source, and an emitter electrode connected to an output node (Data out), and to a capacitor and the collector electrode of a second NPN bipolar transistor, and to the drain electrode of the second NMOS transistor; a fifth NMOS transistor having a drain electrode connected to the source electrode of the second NMOS transistor, and a source electrode connected to the base electrode of the second NPN bipolar transistor, the emitter of which is connected to a ground; and a sixth and a seventh NMOS transistors connected to the base electrode of the second NPN bipolar transistor.
Claim 3
Dependent Claim
302 words
A tri-state output circuit utilizing a BiCMOS inverter circuit comprising: an input node (Data in) connected to each gate electrode of a first PMOS transistor and a first and a second NMOS transistors; the first PMOS transistor having a source electrode connected to a driving voltage source, and a drain electrode connected to the drain electrode of the first NMOS transistor, and to a gate electrode of a third NMOS transistor, and to the source electrode of a second PMOS transistor, a first NPN bipolar transistor having a collector electrode connected to said driving voltage source, and an emitter electrode connected to the drain electrode of the second NMOS transistor, and to a collector electrode of a second NPN bipolar transistor, and to a first capacitor and to an output node (Data out), a third and the second PMOS transistors, a fourth, a fifth and a sixth NMOS transistors, with a tri-state control signal applied to each gate electrode thereof, the fifth NMOS transistor having a source electrode connected to a ground, and a drain electrode connected to the drain electrode of the second PMOS transistor, and to the base electrode of the first NPN bipolar transistor, the third PMOS transistor having a source electrode connected to said driving voltage source, and a drain electrode connected to the drain electrode of the fourth NMOS transistor, and to the gate electrode of a seventh NMOS transistor, the third NMOS transistor having a drain electrode connected to the source electrode of the second NMOS transistor, and to the drain electrode of the seventh NMOS transistor, the seventh NMOS transistor having a source electrode connected to a base electrode of the second NPN bipolar transistor, and to a drain electrode of the sixth NMOS transistor, the source electrode of which is connected to a ground.
Claim 4
Dependent Claim
302 words
A tri-state output circuit utilizing a BiCMOS inverter circuit comprising: an input node (Data in) connected to each gate electrode of a first PMOS transistor and a first and a second NMOS transistors; the first PMOS transistor having a source electrode connected to a driving voltage source, and a drain electrode connected to the drain electrode of the first NMOS transistor, and to a gate electrode of a third NMOS transistor, and to the source electrode of a second PMOS transistor, a first NPN bipolar transistor having a collector electrode connected to said driving voltage source, and an emitter electrode connected to the drain electrode of the second NMOS transistor, and to a collector electrode of a second NPN bipolar transistor, and to a first capacitor and to an output node (Data out), a third and the second PMOS transistors, a fourth, a fifth and a sixth NMOS transistors, with a tri-state control signal applied to each gate electrode thereof, the fifth NMOS transistor having a source electrode connected to a ground, and a drain electrode connected to the drain electrode of the second PMOS transistor, and to the base electrode of the first NPN bipolar transistor, the third PMOS transistor having a source electrode connected to said driving voltage source, and a drain electrode connected to the drain electrode of the fourth NMOS transistor, and to the gate electrode of a seventh NMOS transistor, the third NMOS transistor having a drain electrode connected to the source electrode of the second NMOS transistor, and to the drain electrode of the seventh NMOS transistor, the seventh NMOS transistor having a source electrode connected to a base electrode of the second NPN bipolar transistor, and to a drain electrode of the sixth NMOS transistor, the source electrode of which is connected to a ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |