EP0511643A1
Expired / Lapsed
EP
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Output buffer circuit
Assignee: Toshiba Corp
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Filing: 1992-04-29
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Granted: —
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Expires: 2012-04-29
Abstract
Abstract An output buffer circuit includes a first output buffer (1) having a high output resistance determined by DC specifications, a second output buffer (2) having an output resistance satisfying AC specifications when simultaneously driven with the first output buffer (1), and a control circuit (3) for controlling an operation of the second output buffer (2). An input signal is supplied to the input node of the first output buffer (1), and the output node of the first output buffer (1) is connected to an output terminal (OUT). The output node of the second output buffer (2) is connected to the output terminal (OUT). The control circuit (3) is responsive to the potential of the input signal or of the output terminal (OUT) to control the operation of the second output buffer (2). The control circuit (3) drives the second output buffer (2) when the output from the first output buffer (1) is changed, and sets the output from the second output buffer (2) in the high impedance state when the output from the first output buffer (1) is stationary.
Inventors
- 👤 Hiroshi c/o Int. Pro. Div. KK Toshiba Shigehara
- 👤 Masanori c/o Int. Pro. Div. KK Toshiba Kinugasa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 00:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
131 words
An output buffer circuit for amplifying an input signal and outputting the amplified signal, characterized by comprising a first output buffer (1) having an input node to which the input signal is supplied and an output resistance determined from DC specifications, a second output buffer (2) having an output node connected to an output node of said first output buffer (1) and an output resistance which satisfies AC specifications when said second output buffer (2) is driven simultaneously with said first output buffer, and control means (3) for driving said second output buffer (2) when an output from said first output buffer (1) is changed and setting said output node of said second output buffer (2) in a high-impedance state when the output from said first output buffer (1) is stationary.
Claim 2
Dependent Claim
19 words
A circuit according to claim 1, characterized in that said first output buffer (1) includes a CMOS inverter (IV2).
Claim 3
Dependent Claim
19 words
A circuit according to claim 1, characterized in that said second output buffer (2) includes a MOSFET (P1, N1).
Claim 4
Dependent Claim
20 words
A circuit according to claim 1, characterized in that said second output buffer (2) includes a bipolar transistor (Q1, Q2).
Claim 5
Dependent Claim
31 words
A circuit according to claim 1, characterized in that said control means (3) controls the operation of said second output buffer (2) in response to a level change in input signal.
Claim 6
Dependent Claim
38 words
A circuit according to claim 1, characterized in that said control means (3) controls the operation of said second output buffer (2) in response to a level change of said input node of said first output buffer (1).
Claim 7
Dependent Claim
38 words
A circuit according to claim 1, characterized in that said control means (3) controls the operation of said second output buffer (2) in response to a level change of said output node of said first output buffer (1).
Claim 8
Dependent Claim
153 words
A circuit according to claim 1, characterized in that said second output buffer (2) has a current-source transistor (P1, Q1) connected between a high-potential power supply (Vcc) and said output node of said first output buffer (1), and said control means (3) includes first means (N5) for temporarily setting said current-source transistor (P1, Q1) in an ON state when said output node of said first output buffer (1) is changed from "L" to "H" level, second means (P3, P4) for connecting a control electrode of said current-source transistor (P1, Q1) to said output node of said first output buffer (1) when said output node of said first output buffer (1) is stationary at "H" level, and third means (P2) for connecting said control electrode of said current-source transistor (P1, Q1) to said high-potential power supply (Vcc) when said output node of said first output buffer (1) is changed from "H" to "L" level.
Claim 9
Dependent Claim
18 words
A circuit according to claim 8, characterized in that said current-source transistor is a p-channel MOS transistor (P1).
Claim 10
Dependent Claim
18 words
A circuit according to claim 8, characterized in that said current-source transistor is a pnp bipolar transistor (Q1).
Claim 11
Dependent Claim
153 words
A circuit according to claim 1, characterized in that said second output buffer (2) has a current-sink transistor (N1, Q2) connected between said output node of said first output buffer (1) and a low-potential power supply (Vss), and said control means (3) includes first means (P5) for temporarily setting said current-sink transistor (N1, Q2) in an ON state when said output node of said first output buffer (1) is changed from "H" to "L" level, second means (N4, N3) for connecting a control electrode of said current-sink transistor (N1, Q2) to said output node of said first output buffer (1) when said output node of said first output buffer (1) is stationary at "L" level, and third means (N2) for connecting said control electrode of said current-sink transistor (N1, Q2) to said low-potential power supply (Vss) when said output node of said first output buffer (1) is changed from "L" to "H" level.
Claim 12
Dependent Claim
18 words
A circuit according to claim 11, characterized in that said current-sink transistor is an n-channel MOS transistor (N1).
Claim 13
Dependent Claim
18 words
A circuit according to claim 11, characterized in that said current-sink transistor is an npn bipolar transistor (Q2).
Claim 14
Dependent Claim
203 words
A circuit according to claim 1, characterized in that said second output buffer (2) has a current-source transistor (P1, Q1) connected between a high-potential power supply (Vcc) and said output node of said first output buffer (1) and a current-sink transistor (N1, Q2) connected between said output node and a low-potential power supply (Vss), and said control means (3) includes first means (P3, P4, N5) for temporarily setting said current-source transistor (P1, Q1) in an ON state and connecting a control electrode of said current-sink transistor (N1, Q2) to said low-potential power supply (Vss) when said output node of said first output buffer (1) is changed from "L" to "H" level, second means (P3, P4) for connecting a control electrode of said current-source transistor (P1, Q1) to said output node of said first output buffer (1) when said output node of said first output buffer (1) is stationary at "H" level, and third means (N4, N3, P5) for temporarily setting said current-sink transistor (N1, Q2) in an ON state and connecting said control electrode of said current-source transistor (P1, Q1) to said high-potential power supply (Vcc) when said output node of said first output buffer (1) is changed from "H" to "L" level.
Claim 15
Dependent Claim
28 words
A circuit according to claim 14, characterized in that said current-source transistor is a p-channel MOS transistor (P1), and said current-sink transistor is an n-channel MOS transistor (N1).
Claim 16
Dependent Claim
28 words
A circuit according to claim 14, characterized in that said current-source transistor is a pnp bipolar transistor (Q2), and said current-sink transistor is an npn bipolar transistor (Q2).
Claim 17
Dependent Claim
61 words
A circuit according to claim 8, characterized in that said first means includes switching means (N5, P3, P4) for connecting said control electrode of said current-source transistor (P1, Q1) to either one of a low-potential power supply (Vss) and said output node of said first output buffer (1) when said current-source transistor (P1, Q1) is temporarily set in the ON state.
Claim 18
Dependent Claim
61 words
A circuit according to claim 11, characterized in that said first means includes switching means (P5, N4, N3) for connecting said control electrode of said current-sink transistor (N1, Q2) to either one of a high-potential power supply (Vcc) and said output node of said first output buffer (1) when said current-sink transistor (N1, Q2) is temporarily set in the ON state.
Claim 19
Dependent Claim
81 words
A circuit according to claim 8, characterized in that said control means (30) further comprises a diode means (P3) connected between said control electrode of said current-source transistor (P1, Q1) and said output node of said first output buffer (1), and said control electrode of said current-source transistor (P1, Q1) and said output node of said output buffer (1) are connected through said diode means (P3) when said output node of said first output buffer (1) is set at "H" level.
Claim 20
Dependent Claim
82 words
A circuit according to claim 11, characterized in that said control means (3) further comprises a diode means (N3) connected between said control electrode of said current-sink transistor (N1, Q2) and said output node of said first output buffer (1), and said control electrode of said current-sink transistor (N1, Q2) and said output node of said first output buffer (1) are connected through said diode means (N3) when said output node of said first output buffer (1) is set at "L" level.
Claim 21
Dependent Claim
152 words
A circuit according to claim 14, characterized in that said control means (3) further comprises a first diode means (P3) connected between said control electrode of said current-source transistor (P1, Q1) and said output node of said first output buffer (1) and a second diode means (N3) connected between said control electrode of said current-sink transistor (N1, Q2) and said output node of said first output buffer (1), said control electrode of said current-source transistor (P1, Q1) and said output node of said first output buffer (1) are connected through said first diode means (P3) when said output node of said first output buffer (1) is at "H" level, and said control electrode of said current-sink transistor (N1, Q2) and said output node of said first output buffer (1) are connected through said second diode means (N3) when said output node of said first output buffer (1) is set at "L" level.
Claim 22
Dependent Claim
117 words
A circuit according to claim 1, characterized in that said control means (3) includes first switching means (P2) connected between said high-potential power supply (Vcc) and said control electrode of said current-source transistor (P1, Q1), second switching means (P3, P4) connected between said control electrode of said current-source transistor (P1, Q1) and said output node, third switching means (N5) connected between said control electrode of said current-source transistor (P1, Q1) and either one of said low-potential power supply (Vss) and said output node of said first output buffer (1), and a control circuit (IV1, DL, IV3, NA, NR) for controlling said first, second, and third switching means (P2; P3, P4; N5) in accordance with a predetermined order.
Claim 23
Dependent Claim
123 words
A circuit according to claim 1, characterized in that said control means (3) includes first switching means (N2) connected between said control electrode of said current-sink transistor (N1, Q2) and a low-potential power supply (Vss), second switching means (N3, N4) connected between said control electrode of said current-sink transistor (N1, Q2) and said output node of said first output buffer (1), third switching means (P5) connected between said control electrode of said current-source transistor (N1, Q2) and either one of said low-potential power supply (Vss) and said output node of said first output buffer (1), and a control circuit (IV1, DL, IV3, NA, NR) for controlling said first, second, and third switching means (N2; N3, N4; P5) in accordance with a predetermined order.
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