Output circuit device with stabilized potential

Claim 2

An output circuit device which comprises: (a) first circuit means (1) for inverting an input signal; (b) load capacitor means (13) for charging and discharging electric charge of an output signal from said first circuit means (1); and (c) second circuit means (3) connected to said first circuit means (1) for controlling the charging and discharging speed of said load capacitor means in accordance with the voltage of the output signal.

Claim 3

An output circuit device as claimed in claim 1, wherein said first circuit means (1) having a first type MOS transistor and a second type MOS transistor connected in parallel to each other the source of said first type MOS transistor being connected to a first power supply and the source of said second type MOS transistor being connected to a second power supply, and the gates of said first and second'type MOS transistors being connected in parallel to an input terminal.

Claim 4

An output circuit device as claimed in claim 2, wherein said second circuit means (3) having at least a first type MOS transistor and a second type MOS transistor connected in parallel to each other, said second circuit means being connected between the output of said first circuit means and an output terminal, the source of the first type MOS transistor in the second circuit means being connected to the first power supply, the source of the second type MOS transistor being connected to the second power supply, and said first and second type MOS transistors having a first threshold voltage level.

Claim 5

An output circuit device as claimed in claim 3, wherein said load capacitor means is connected between the output terminal and the ground potential for charging and discharging electric charge of an output signal.

Claim 6

An output circuit device as claimed in claim 4, wherein the first type MOS transistor is a P-MOS transistor and the second type MOS transistor is N-MOS transistor, the first power supply is a high voltage source, and the second power supply is a low voltage source.

Claim 7

An output circuit device as claimed in claim 4, further comprises control means (15) connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal.

Claim 8

An output circuit device as claimed in claim 6, wherein said control means comprises a first type MOS transistor (21) and a second type MOS transistor (23) connected in parallel to each other.

Claim 9

An output circuit device as claimed in claim 6, wherein said control means consists of NAND (27) and NOR (29) gates connected in parallel to each other and an inverter (25) connected between the input terminal of said first circuit means and one input of said NOR gate.

Claim 10

An output circuit device as claimed in claim 6, wherein said control means consists of NAND (33) and NOR (31) gates connected in parallel to each other, a first inverter (35) connected between the output of said first circuit means and each one input of said NAND and NOR gates, and second (37) and third (39) inverters connected between each input of said second circuit means and each output of said NAND and NOR gates respectively.

Claim 11

An output circuit device as claimed in claim 6, wherein said control means comprises NAND (43) and NOR (45) gates connected in parallel to each other, and said output circuit device further comprises an inverter (41), one terminal of which is connected to the input of said first circuit device and the other terminal of which is connected to one input of said NOR gate and to the input terminal.

Claim 12

ll. An output circuit device as claimed in claim 6, wherein said second circuit means comprises two pairs (3, 3') of the first and second type MOS transistors, each drain of which being connected to each other, said control means comprises two pairs of NAN D and NOR gates, each output of said NAND and NOR gate pairs being connected to each of the control gate of the ifrst and second type MOS transistor pairs in the second circuit means and said output circuit device further comprises an inverter (47) connected between the input terminal of said first circuit means and each one input of said NAND and NOR gate pairs in the control means, each of said NAND and NOR gate pairs having first and second threshold levels respectively.

Claim 13

An output circuit device as claimed in claim 6, wherein said control means consists of NAND and NOR gates (63, 65), each output of which being connected to each of the MOS transistors in the second circuit means, an EXCLUSIVE-OR and EXCLUSIVE-NOR gate pair, each output of which being connected to each input of said NAND and NOR gates respectively, and inverter (57) connected between the input terminal of the first circuit means and the other input of said NOR gate.

Claim 14

An output circuit device as claimed in claim 6, wherein said control means comprises NAND and NOR gates (67, 69), each output of which being connected to each of the first and second type MOS transistors respectively of the second circuit means and each input of said NAND and NOR gates being connected in parallel to each other, a first inverter (71) connected between the input terminal of the first circuit means and one input of said NAND gate, and a second inverter (73) connected between the output of said first circuit means and the other input of said NAND gate.

Claim 15

An output circuit device as claimed in claim 6, wherein said control means consists of a NOR (73) and NAND (75) gate pair and first (77) and second (79) inverters connected respectively between each output of said NOR and NAND gate pair and each control gate of the first and second type MOS transistors in the second circuit means, one input of said NAND and NOR gate pair being connected to the output of the first circuit means and the other input of said NAND and NOR gate pair being connected to the input terminal of the first circuit means.

Claim 16

An output circuit device as claimed in claim 6, wherein said control means consists of a NAND (43) and NOR (45) pair and a first inverter (81), each output of said NAND and NOR gate pair being connected to each control gate of the first and second type MOS transistors in the second circuit means, and each input of said NAND and NOR gate pair being connected in parallel to each other and to the output of said first inverter, and said output circuit device further comprises second inverter (41) connected between the control gates of the first circuit means and the input terminal which is in turn connected to one input of said NAND and NOR gate pair.

Claim 17

An output circuit device as claimed in claim 6, wherein said control means consists of a NAND (83) and NOR (85) gate pair and first (87) and second (89) inverters, each of one of the inputs of said NAND and NOR gate pair being connected in parallel to each other and to the output terminal of the first circuit means, each output of said NAND and NOR gate pair being connected to each of the control gates of the first and second type MOS transistors in the second circuit means, and each input of said first and second inverters being connected to each of the input terminals respectively while each output of said first and second inverters being connected to each of the other inputs of said NAND and NOR gate pair respectively.

Claim 18

An output circuit device as claimed in claim 16, wherein said control means further comprises a third inverter (91) connected between the output terminal of the first circuit means and the one input of said NAND and NOR gate pair.

Claim 19

An output circuit device which comprises: (a) first circuit means (1) having a first type MOS transistor and a second type MOS transistor connected in parallel to each other, (b) the source of said first type MOS transistor being connected to a first power supply and the source of said second type MOS transistor being connected to a second power supply; (c) second circuit means (3) having at least a first type MOS transistor and a second type MOS transistor connected in parallel to each other, (d) said second circuit means being connected between the output of said first circuit means and an output terminal, the source of the first type MOS transistor in the second circuit means being connected to the first power supply, the source of the second type MOS transistor being connected to the second power supply, and said first and second type MOS transistors having a first threshold voltage level; and (e) a load capacitor means is connected between the output terminal and the ground potential for charging and discharging electric charge of an output signal, thereby suppressing undershoot and overshoot phenomena when the output potential of the first and second type MOS transistors in the second circuit means reaches the threshold voltage level.

Claim 20

An output circuit device which comprises: (a) first circuit means (1) having a first type MOS transistor and a second type MOS transistor connected in parallel to each other, (b) the source of said first type MOS transistor being connected to a first power supply and the source of said second type MOS transistor being connected to a second power supply; (c) second circuit means (3) having at least a first type MOS transistor and a second type MOS transistor connected in parallel to each other, (d) said second circuit means being connected between the output of said first circuit means and an output terminal, the source of the first type MOS transistor in the second circuit means being connected to the first power supply, the source of the second type MOS transistor being connected to the second power supply, and said first and second type MOS transistors having a first threshold voltage level; and (e) a load capacitor means is connected between the output terminal and the ground potential for charging and discharging electric charge of an output signal, thereby suppressing undershoot and overshoot phenomena when the output potential of the first and second type MOS transistors in the second circuit means reaches the threshold voltage level.

Claim 21

An output circuit device as claimed in claim 18, wherein the first type MOS transistor is a P-MOS transistor and the second type MOS transistor is N-MOS transistor, the first power supply is a high voltage source, and the second power supply is a low voltage source.