US5220205A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output circuit of an integrated circuit having immunity to power source fluctuations
Assignee: Toshiba Corp
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Filing: 1991-12-18
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Granted: 1993-06-15
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Expires: 2011-12-18
Abstract
Abstract A series circuit of two P-channel transistors and a series circuit of two N-channel transistors are used respectively as a latch circuit which temporarily latches an input signal until the power source fluctuation caused by the change of the output signal is suppressed. The gates of the transistors of the two series-circuits are supplied with the output signal of an output-stage circuit and a delayed output signal obtained by delaying the above output signal so that either one of the two series-circuits can be controlled to be turned on so as to temporarily latch an input signal in a dynamic manner until the power source fluctuation is suppressed. Since the gate signals to the transistors of the two series-circuits are directly supplied without being passed through single-channel type transfer gates, a sufficiently large bias voltages are supplied to the gate of the latch circuits even under the low power source voltage. Thus, the output circuit capable of providing a desired operation characteristic even under the low operation voltage can be realized.
Inventors
- 👤 Hiroshi Shigehara
- 👤 Masanori Kinugasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:41
CPC Classifications
G; G11; G11C; G11C7/00; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356165; H03K3/01; H03K3/013
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
160 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the output terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of said output-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 2
Dependent Claim
160 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the output terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of said output-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 3
Dependent Claim
111 words
A semiconductor integrated circuit according to claim 1, wherein said output-stage circuit comprises an inverter circuit of an odd number of inverter stages for inverting said output signal of said intermediate-stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for delaying said output signal of said output-stage circuit by a preset period of time and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 4
Dependent Claim
113 words
A semiconductor integrated circuit according to claim 1, wherein said output-stage circuit comprises an inverter circuit of an odd number of inverter stages for inverting said output signal of said intermediate-stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for inverting and delaying said output signal of said output-stage circuit by a preset period of time, and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 5
Dependent Claim
160 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the outcome terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of said intermediate-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 6
Dependent Claim
160 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the outcome terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of said intermediate-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 7
Dependent Claim
113 words
A semiconductor integrated circuit according to claim 4, wherein said output stage circuit comprises an inverter circuit for an odd number of inverter stages for inverting said output signal of said intermediate stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for delaying said output signal of said intermediate-stage circuit by a preset period of time and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 8
Dependent Claim
114 words
A semiconductor integrated circuit according to claim 4, wherein said output-stage circuit comprises an inverter circuit of an odd number of inverter stages for inverting said output signal of said intermediate-stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for inverting and delaying said output signal of said intermediate-stage circuit by a preset period of time, and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to the gates of said at least two transistors of each of said first and second latch circuits.
Claim 9
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the output terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of an intermediate output signal of said output-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 10
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a power source having first and second power source wirings, for supplying an operation voltage to respective circuits; an input-stage circuit for receiving an input signal; an intermediate-stage circuit for inverting an output signal of said input-stage circuit; an output-stage circuit for supplying either an inverted or a non-inverted signal of an output signal of said intermediate-stage circuit to an output terminal; a first latch circuit having at least two P-channel transistors serially connected between said first power source wiring and an output terminal of said input-stage circuit; a second latch circuit having at least two N-channel transistors serially connected between said second power source wiring and the output terminal of said input-stage circuit; and a latch control circuit for supplying said output signal of said intermediate-stage circuit and a delayed output signal of an intermediate output signal of said output-stage circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 11
Dependent Claim
113 words
A semiconductor integrated circuit according to claim 7, wherein said output stage circuit comprises an inverter circuit of an odd number of inverter stages for inverting said output signal of said intermediate-stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for delaying said intermediate output signal of said output-stage circuit by a preset period of time and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
Claim 12
Dependent Claim
114 words
A semiconductor integrated circuit according to claim 7, wherein said output-stage circuit comprises an inverter circuit of an odd number of inverter stages for inverting said output signal of said intermediate-stage circuit and an output buffer circuit for buffer-amplifying and outputting an output signal of said inverter circuit to said output terminal; and said latch control circuit comprises a delay circuit for inverting and delaying said intermediate output signal of said output-stage circuit by a preset period of time, and supplies said output signal of said intermediate-stage circuit and an output signal of said delay circuit respectively to gates of said at least two transistors of each of said first and second latch circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |