Dynamic input latch

Claim 2

A integrated circuit having power supply and ground nodes comprising: (a) an input stage for receiving digital input signals; (b) an output stage for transmitting output signals; (c) an intermediate stage coupled between said input and output stages for transforming input signals into desirable output signals; and (d) a latching circuit for use with an input signal having two states, operable upon a transition to a first state, providing a first predetermined voltage level at the input of said intermediate stage for a predetermined time, and, upon transition to a second state, providing a second predetermined voltage at the input to the intermediate stage for said predetermined time wherein said predetermined time is less than the time between transition of the input signal states.

Claim 3

The circuit of claim 1 wherein said latching circuit maintains said first predetermined voltage level by engaging a switch between at least one reference voltage source and said input to said intermediate stage.

Claim 4

The circuit of claim 1 wherein said latching circuit maintains said second predetermined voltage level by engaging a switch between at least one ground node and said input to said intermediate stage.

Claim 5

The circuit of claim 1 wherein said latching circuit detects a change in voltage from said output stage.

Claim 6

A circuit having power supply and ground nodes comprising: (a) an input stage for receiving digital signals from outside sources; (b) an output stage for transmitting output signals, (c) a plurality of inverting and non-inverting stages disposed between said input stage and said output stage; and (d) a latching circuit for use with an input signal having two states, operable upon an input signal transition to a first state, to provide a first determined voltage to a selected input of one of said inverting or non inverting stages for a predetermined time interval, and upon transition of said input signal to a second state to provide a second predetermined voltage to said selected input for said predetermined time interval wherein said predetermined time interval is less than the time between transitions of said input signal states.

Claim 7

A circuit having power supply and ground nodes comprising: (a) an input stage for receiving digital signals from outside sources; (b) an output stage for transmitting output signals, (c) a plurality of inverting and non-inverting stages disposed between said input stage and said output stage; and (d) a latching circuit for use with an input signal having two states, operable upon an input signal transition to a first state, to provide a first determined voltage to a selected input of one of said inverting or non inverting stages for a predetermined time interval, and upon transition of said input signal to a second state to provide a second predetermined voltage to said selected input for said predetermined time interval wherein said predetermined time interval is less than the time between transitions of said input signal states.

Claim 8

The circuit of claim 5 wherein said latching circuit maintains said first predetermined voltage level by engaging a switch between at least one reference voltage source and said input to said intermediate stage.

Claim 9

The circuit of claim 5 wherein said latching circuit maintains said second predetermined voltage level by engaging a switch between at least one ground node and said input to said intermediate stage.

Claim 10

The circuit of claim 5 wherein said latching circuit detects a change in voltage from said output stage.

Claim 11

An output circuit comprising: an input stage for receiving input signals; an output stage for transmitting output signals; first and second inverting stages serially diposed between said input stage and said output stage; a voltage sensing device disposed after said second inverting stage; a switching device disposed between a predetermined voltage source and the input to said second inverting stage, said switching device enabling a flow of charge between the voltage source and said input stage to said second inverting stage upon detection of a voltage change by said voltage sensing device; and a disabling device disposed between said output stage and said switching device, said disabling device operable for disabling the flow of charge between the predetermined voltage source and said input stage to said second inverting stage after a predetermined time interval has elapsed since a change in the output signal.

Claim 12

An output circuit comprising: an input stage for receiving input signals; an output stage for transmitting output signals; first and second inverting stages serially diposed between said input stage and said output stage; a voltage sensing device disposed after said second inverting stage; a switching device disposed between a predetermined voltage source and the input to said second inverting stage, said switching device enabling a flow of charge between the voltage source and said input stage to said second inverting stage upon detection of a voltage change by said voltage sensing device; and a disabling device disposed between said output stage and said switching device, said disabling device operable for disabling the flow of charge between the predetermined voltage source and said input stage to said second inverting stage after a predetermined time interval has elapsed since a change in the output signal.

Claim 13

The output circuit of claim 9 wherein said voltage sensing device is a first transistor with its source connected to the output of the second inverting stage and its drain connected to the switching device.

Claim 14

The output circuit of claim 10 wherein said voltage sensing device further comprises a plurality of delay devices connected between said output stage and said first transistor.

Claim 15

The output circuit of claim 10 wherein said switching device comprises a second transistor, said second transistor having its source connected to said predetermined voltage source and having its drain connected to the input to said second inverting stage.

Claim 16

The output circuit of claim 12 wherein said second transistor has its gate connected to said voltage sensing device.

Claim 17

The output circuit of claim 12 wherein said disabling device comprises a third transistor, said third transistor having its source connected to said predetermined voltage source and having its drain connected to the switching device.

Claim 18

The output circuit of claim 14 wherein said disabling device further comprises a plurality of delay devices disposed between said output stage and said third transistor.