US4554467A
Expired / Lapsed
US
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CMOS Flip-flop
Assignee: Motorola Solutions Inc
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Filing: 1983-06-22
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Granted: 1985-11-19
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Expires: 2003-06-22
Abstract
Abstract A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.
Inventors
- 👤 Herchel A. Vaughn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:12
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
222 words
A CMOS flip-flop, comprising: a first controllable switch, having an input for receiving an input signal, and an output, for coupling the input signal to the output when a clock signal is at or near a voltage present at a first power supply terminal and for preventing the input signal from reaching the output when the clock signal is at or near a voltage at a second power supply terminal; a first inverter having an input coupled to the output of the first controllable switch, and an output; a first P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the first inverter, and a second current electrode directly connected to the input of the first inverter with no intervening elements therebetween; a first N channel transistor having a first current electrode coupled to the input of the first inverter, a control electrode coupled to the output of the first inverter, and a second current electrode; and a second N channel transistor having a first current electrode coupled to the second current electrode of the first N channel transistor, a control electrode for receiving a signal complementary to the clock signal, and a second current electrode coupled to the second power supply terminal.
Claim 2
Dependent Claim
222 words
A CMOS flip-flop, comprising: a first controllable switch, having an input for receiving an input signal, and an output, for coupling the input signal to the output when a clock signal is at or near a voltage present at a first power supply terminal and for preventing the input signal from reaching the output when the clock signal is at or near a voltage at a second power supply terminal; a first inverter having an input coupled to the output of the first controllable switch, and an output; a first P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the first inverter, and a second current electrode directly connected to the input of the first inverter with no intervening elements therebetween; a first N channel transistor having a first current electrode coupled to the input of the first inverter, a control electrode coupled to the output of the first inverter, and a second current electrode; and a second N channel transistor having a first current electrode coupled to the second current electrode of the first N channel transistor, a control electrode for receiving a signal complementary to the clock signal, and a second current electrode coupled to the second power supply terminal.
Claim 3
Dependent Claim
183 words
The CMOS flip-flop of claim 1, comprising: a second controllable switch clocked by the signal complementary to the clock signal and having an input coupled to the output of the first inverter, and an output; a second inverter having an input coupled to the output of the second controllable switch, and an output; a second P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the second inverter, and a second current electrode directly connected to the input of the second inverter with no intervening elements therebetween; a third N channel transistor having a first current electrode coupled to the input of the second inverter, a control electrode coupled to the output of the second inverter, and a second current electrode; and a fourth N channel transistor having a first current electrode coupled to the second current electrode of the third N channel transistor, a control electrode for receiving the clock signal, and a second current electrode coupled to the second power supply terminal.
Claim 4
Dependent Claim
29 words
The CMOS flip-flop of claim 2 wherein the first and second controllable switches are transmission gates clocked by the clock signal and the signal complementary to the clock signal.
Claim 5
Dependent Claim
201 words
A CMOS flip-flop, comprising: a first controllable switch, having an input for receiving an input signal, and an output, for coupling the input signal to the output when a clock signal is at or near a voltage present at a first power supply terminal and for preventing the input signal from reaching the output when the clock signal is at or near a voltage at a second power supply terminal; a first inverter having an input coupled to the output of the first controllable switch, and an output; a first P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the first inverter, and a second current electrode directly connected to the input of the first inverter with no intervening elements therebetween; and a first pair of series-coupled N channel transistors coupled between the input of the first inverter and the second power supply terminal, wherein one of the first pair has a control electrode coupled to the output of the first inverter and the other of the pair has a control electrode for receiving a signal complementary to the clock signal.
Claim 6
Dependent Claim
201 words
A CMOS flip-flop, comprising: a first controllable switch, having an input for receiving an input signal, and an output, for coupling the input signal to the output when a clock signal is at or near a voltage present at a first power supply terminal and for preventing the input signal from reaching the output when the clock signal is at or near a voltage at a second power supply terminal; a first inverter having an input coupled to the output of the first controllable switch, and an output; a first P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the first inverter, and a second current electrode directly connected to the input of the first inverter with no intervening elements therebetween; and a first pair of series-coupled N channel transistors coupled between the input of the first inverter and the second power supply terminal, wherein one of the first pair has a control electrode coupled to the output of the first inverter and the other of the pair has a control electrode for receiving a signal complementary to the clock signal.
Claim 7
Dependent Claim
163 words
The CMOS flip-flop of claim 4 further comprising: a second controllable switch clocked by the signal complementary to the clock signal and having an input coupled to the output of the first inverter, and an output: a second inverter having an input coupled to the output of the second controllable switch, and an output; a second P channel transistor having a first current electrode directly connected to the first power supply terminal with no intervening elements therebetween, a control electrode coupled to the output of the second inverter, and a second current electrode directly connected to the input of the second inverter with no intervening elements therebetween; and a second pair of series-coupled N channel transistors coupled between the input of the second inverter and the second power supply terminal, wherein one of the second pair has a control electrode coupled to the output of the second inverter and the other of the pair has a control electrode for receiving the clock signal.
Claim 8
Dependent Claim
30 words
The CMOS flip-flop of claim 5 wherein the first and second controllable switches are transmission gates, each clocked by the clock signal and the signal complementary to the clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |