Memory cell

Claim 2

A memory cell comprising, in combination: first and second inverters, each having an input node and an output node, each coupled at its output node to the input node of the other; a digit line; means responsive to a read command for coupling said digit line to the input node of the first of said inverters; and means responsive to a strobe signal concurrent with said read command for disconnecting the input node of the second of said inverters from the first of said inverters.

Claim 3

The combination set forth in claim 1 wherein each inverter comprises two transistors, the first of said two transistors a PMOS device and the second of said two transistors an NMOS device, the conduction paths of said two transistors connected in series between two operating voltage terminals, the gate electrodes of said two transistors connected, in common, to an input node, and the point at which the two conduction paths are coupled connected to an output node.

Claim 4

The combination set forth in claim 2 wherein said means responsive to a strobe signal comprises two normally closed switch elements, one between the PMOS transistor conduction path of said first inverter and the first inverter output node and the other between the conduction path of the NMOS transistor conduction path of said first inverter and the first inverter output node.

Claim 5

The combination set forth in claim 3 wherein said switch elements comprise first and second MOS transistors, each transistor being of the same conductivity type.

Claim 6

The combination of claim 2 wherein said means responsive to a strobe comprises a normally closed switch element coupled between a common connection of said first inverter PMOS and NMOS conduction paths and said first inverter output node.

Claim 7

The combination of claim 5 wherein said switch element comprises an MOS transistor.

Claim 8

In a memory array having M rows and N columns intersecting said rows, where M and N are integers, said array comprising, in combination: N column digit lines; M sets of row address lines; M times N memory cells, each cell coupled between a digit line and the corresponding intersecting row address set, said cell comprising, in combination: first and second inverters, each having an input node and an output node, each coupled at its output node to the input node of the other; means connected to a said row address set for coupling said digit line to the input node of the first of said inverters; and means responsive to a strobe signal concurrent with said read command for disconnecting the input node of the second of said inverters from the first of said inverters.

Claim 9

In a memory array having M rows and N columns intersecting said rows, where M and N are integers, said array comprising, in combination: N column digit lines; M sets of row address lines; M times N memory cells, each cell coupled between a digit line and the corresponding intersecting row address set, said cell comprising, in combination: first and second inverters, each having an input node and an output node, each coupled at its output node to the input node of the other; means connected to a said row address set for coupling said digit line to the input node of the first of said inverters; and means responsive to a strobe signal concurrent with said read command for disconnecting the input node of the second of said inverters from the first of said inverters.

Claim 10

The combination set forth in claim 7 wherein each inverter comprises two transistors, the first of said two transistors a PMOS device and the second of said two transistors an NMOS device, the conduction paths of said two transistors connected in series between two operating voltage terminals, the gate electrodes of said two transistors connected, in common, to an input node, and the point at which the two conduction paths are coupled connected to an output node.