Patent US5386136A successfully refreshed from Google Patents.
US5386136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Lightly-doped drain MOSFET with improved breakdown characteristics
Assignee: Vishay Siliconix Inc
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Filing: 1991-05-06
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Granted: 1995-01-31
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Expires: 2011-05-06
Abstract
Abstract An LDD lateral DMOS transistor is provided in a lightly-doped epitaxial layer of a first conductivity above a substrate of the same conductivity. A highly-doped buried layer of the first conductivity is provided under the LDD lateral DMOS transistor to relieve crowding of electrical equipotential distribution beneath the silicon surface. In one embodiment, a gate plate is provided above the gate and the gate-edge of the drift region. An optional N-well provides further flexibility to shape electric fields beneath the silicon surface. The buried layer can also reduce the electric field in a LDD lateral diode and improves cathode-to-anode reversed-recovery characteristics.
Inventors
- 👤 Richard K. Williams
- 👤 Michael E. Cornell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:26
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/835; H10D84/85; H10D84/856; H10D30/64; H10D30/65; H10D62/124; H10D62/126; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/00; H10D64/111; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
217 words
A lateral DMOS transistor structure, comprising: an epitaxial layer of a first conductivity formed on a surface of a substrate of said first conductivity; a source region formed in said epitaxial layer, said source region having a conductivity opposite said first conductivity; a body region of said first conductivity formed in said epitaxial layer adjacent said source region having a portion of said body region exposed on a surface of said epitaxial layer away from said surface of said substrate; a drift region of said second conductivity formed in said epitaxial layer and spaced from said source and said body regions by an exposed portion of said epitaxial layer on the surface of said epitaxial layer away from said surface of said substrate, such that said exposed portion of said body region and said exposed portion of said epitaxial layer form a channel region between said source region and said drift region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region away from said channel region; a gate region formed above said channel region; and a buried layer of said first conductivity having a dopant concentration substantially higher than the dopant concentration of said substrate, and having a portion located underneath the interface between said channel and said drift regions.
Claim 2
Dependent Claim
217 words
A lateral DMOS transistor structure, comprising: an epitaxial layer of a first conductivity formed on a surface of a substrate of said first conductivity; a source region formed in said epitaxial layer, said source region having a conductivity opposite said first conductivity; a body region of said first conductivity formed in said epitaxial layer adjacent said source region having a portion of said body region exposed on a surface of said epitaxial layer away from said surface of said substrate; a drift region of said second conductivity formed in said epitaxial layer and spaced from said source and said body regions by an exposed portion of said epitaxial layer on the surface of said epitaxial layer away from said surface of said substrate, such that said exposed portion of said body region and said exposed portion of said epitaxial layer form a channel region between said source region and said drift region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region away from said channel region; a gate region formed above said channel region; and a buried layer of said first conductivity having a dopant concentration substantially higher than the dopant concentration of said substrate, and having a portion located underneath the interface between said channel and said drift regions.
Claim 3
Dependent Claim
27 words
A structure as in claim 1, further comprising a gate plate located above said gate region and extending over said interface between said channel and drift regions.
Claim 4
Dependent Claim
27 words
A structure as in claim 1, further comprising a drain plate located above said drain region and extending over the interface between said drift and drain regions.
Claim 5
Dependent Claim
25 words
A structure as in claim 1, further comprising a deep diffusion region of said first conductivity in said epitaxial layer and adjacent said body region.
Claim 6
Dependent Claim
25 words
A structure as in claim 1, further comprising a deep diffusion region of said second conductivity in said epitaxial layer and adjacent said drain region.
Claim 7
Dependent Claim
18 words
A structure as in claim 1, wherein said first conductivity is p-type and said second conductivity is n-type.
Claim 8
Dependent Claim
19 words
A structure as in claim 1, wherein said lateral DMOS transistor structure is substantially annular about said drain region.
Claim 9
Dependent Claim
193 words
A lateral DMOS transistor structure, comprising: an epitaxial layer of a first conductivity formed on a surface of a substrate of first conductivity; a gate region above said epitaxial layer, said gate region defining, on surface of said epitaxial layer, a channel region underneath said gate region; a source region of a second conductivity opposite said first conductivity in said epitaxial layer having a portion exposed on the surface of said epitaxial layer adjacent said channel region; a body region of said first conductivity formed in said channel region in said epitaxial layer adjacent said source region; a drift region of said second conductivity formed in said epitaxial layer adjacent said channel region away from said body region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region; an oxide region adjacent said drift region, being located away from the interface between said channel region and said drift region; and a buried layer of said first conductivity having a dopant concentration substantially higher than the dopant concentration of said substrate and having a first portion located underneath the interface between said drift region and said oxide region.
Claim 10
Dependent Claim
193 words
A lateral DMOS transistor structure, comprising: an epitaxial layer of a first conductivity formed on a surface of a substrate of first conductivity; a gate region above said epitaxial layer, said gate region defining, on surface of said epitaxial layer, a channel region underneath said gate region; a source region of a second conductivity opposite said first conductivity in said epitaxial layer having a portion exposed on the surface of said epitaxial layer adjacent said channel region; a body region of said first conductivity formed in said channel region in said epitaxial layer adjacent said source region; a drift region of said second conductivity formed in said epitaxial layer adjacent said channel region away from said body region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region; an oxide region adjacent said drift region, being located away from the interface between said channel region and said drift region; and a buried layer of said first conductivity having a dopant concentration substantially higher than the dopant concentration of said substrate and having a first portion located underneath the interface between said drift region and said oxide region.
Claim 11
Dependent Claim
26 words
A structure as in claim 8, wherein said buried layer having a second portion located underneath said interface between said channel region and said drift region.
Claim 12
Dependent Claim
55 words
A structure as in claim 8, further comprising a gate plate above said gate region extending over said interface between said channel region and said drift region and extending along the boundary of said drift region to provide a portion of said gate plate above the interface between said oxide region and said drift region.
Claim 13
Dependent Claim
25 words
A structure as in claim 8, further comprising a deep diffusion region of said first conductivity formed in said epitaxial layer adjacent said body region.
Claim 14
Dependent Claim
25 words
A structure as in claim 8, further comprising a deep diffusion region of said second conductivity formed in said epitaxial layer adjacent said drain region.
Claim 15
Dependent Claim
18 words
A structure as in claim 8, wherein said first conductivity is p-type and said second conductivity is n-type.
Claim 16
Dependent Claim
211 words
An LDD DMOS transistor structure, comprising: a buried layer of a first conductivity formed on a surface of a substrate of said first conductivity; said buried layer having a dopant concentration substantially higher than the dopant concentration of said substrate; an epitaxial layer of said first conductivity formed on said surface of said substrate; a drift region of a second conductivity formed in said epitaxial layer, a portion of the boundary of said drift region located above said buried layer; an oxide layer formed above said drift region; a gate formed above said epitaxial layer such that a portion of said epitaxial layer underneath said gate is adjacent said portion of the boundary of said drift region, said portion of said epitaxial layer forming a channel region; a body region formed in said epitaxial layer, said body region having a portion in said channel region exposed on a surface of said epitaxial layer, said exposed portion of said body region located away from said drift region; a source region of said second conductivity formed in said epitaxial layer adjacent said channel region and said exposed portion of said body region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region away from said channel region.
Claim 17
Dependent Claim
211 words
An LDD DMOS transistor structure, comprising: a buried layer of a first conductivity formed on a surface of a substrate of said first conductivity; said buried layer having a dopant concentration substantially higher than the dopant concentration of said substrate; an epitaxial layer of said first conductivity formed on said surface of said substrate; a drift region of a second conductivity formed in said epitaxial layer, a portion of the boundary of said drift region located above said buried layer; an oxide layer formed above said drift region; a gate formed above said epitaxial layer such that a portion of said epitaxial layer underneath said gate is adjacent said portion of the boundary of said drift region, said portion of said epitaxial layer forming a channel region; a body region formed in said epitaxial layer, said body region having a portion in said channel region exposed on a surface of said epitaxial layer, said exposed portion of said body region located away from said drift region; a source region of said second conductivity formed in said epitaxial layer adjacent said channel region and said exposed portion of said body region; a drain region of said second conductivity formed in said epitaxial layer adjacent said drift region away from said channel region.
Claim 18
Dependent Claim
28 words
A structure as in claim 14, further comprising a deep diffusion region of said first conductivity in said epitaxial layer adjacent said body region and said buried layer.
Claim 19
Dependent Claim
27 words
A structure as in claim 14, wherein said gate extends over said oxide layer forming a gate plate near the interface between said channel and drift regions.
Claim 20
Dependent Claim
153 words
A self-isolated diode structure, comprising: a buried layer of a first conductivity formed on a surface of a substrate of said first conductivity; an epitaxial layer of said first conductivity formed on said surface of said substrate; an oxide layer formed on top of said epitaxial layer, said oxide layer partially covering said epitaxial layer, and exposing first and second regions of said epitaxial layer, a portion of the boundary of said first region being located above said buried layer; a drift region of a second conductivity formed in said first region of said epitaxial layer adjacent said oxide layer at said portion of said boundary; a cathode region of said second conductivity formed in said first region of said epitaxial layer adjacent said drift region away from said portion of said boundary, and an anode region of said first conductivity in said second region of said epitaxial layer adjacent said oxide layer.
Claim 21
Dependent Claim
153 words
A self-isolated diode structure, comprising: a buried layer of a first conductivity formed on a surface of a substrate of said first conductivity; an epitaxial layer of said first conductivity formed on said surface of said substrate; an oxide layer formed on top of said epitaxial layer, said oxide layer partially covering said epitaxial layer, and exposing first and second regions of said epitaxial layer, a portion of the boundary of said first region being located above said buried layer; a drift region of a second conductivity formed in said first region of said epitaxial layer adjacent said oxide layer at said portion of said boundary; a cathode region of said second conductivity formed in said first region of said epitaxial layer adjacent said drift region away from said portion of said boundary, and an anode region of said first conductivity in said second region of said epitaxial layer adjacent said oxide layer.
Claim 22
Dependent Claim
28 words
A structure as in claim 17, further comprising a deep diffusion region of said first conductivity in said epitaxial layer adjacent said anode region and said buried layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |