EP0114435A1
Expired / Lapsed
EP
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Lateral DMOS transistor devices suitable for sourcefollower applications
Assignee: Koninklijke Philips NV
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Filing: 1983-12-15
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Granted: —
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Expires: 2003-12-15
Abstract
Abstract A lateral DMOS includes an intermediate semiconductor layer (16) of the same conductivity type as the channel region (20) which extends laterally from the channel region to beneath the drain contact region (24) of the device. This intermediate semiconductor layer (16) substantially improves the punchthrough and avalanche breakdown characteristics of the device, thus permitting operation in the source-follower mode, while also providing a compact structure which features a relatively low normalized "on" resistance.
Inventors
- 👤 Sel Colak
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 20:35
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/109; H10D62/111; H10D12/00; H10D12/411; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D84/00; H10D84/101; H10D84/151; H10D30/611; H10D62/13; H10D62/141; H10D62/142; H10D62/17; H10D62/393
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
238 words
A lateral DMOS transistor comprising a semiconductor substrate of a first conductivity type, a layer-shaped region on a first major surface of said substrate and forming a pn-junction with said substrate, a first surface-adjoining channel region of said first conductivity type in said layer-shaped region, a surface-adjoining source region of a second conductivity type opposite to that of the first in said channel region, a first surface-adjoining drain contact region of said second conductivity type in said layer-shaped region and spaced apart from said first channel region, an insulating layer on the surface of said transistor and covering at least that portion of the first surface-adjoining channel region located between said source region and said layer-shaped region, a first gate electrode on said insulating layer over at least said portion of the first channel region, and source-and first drain electrodes connected respectively to the source-and first drain contact regions, characterized in that said layer-shaped region is composed of a first semiconductor layer of said second conductivity type on said substrate, a second semiconductor layer of said first conductivity type on said first layer and a third surface-adjoining semiconductor layer of said second conductivity type on said second layer, in that said first surface-adjoining channel region is connected to said second layer, and in that an extended drain region is formed from a portion of said third layer between said first drain contact region and said first channel region.
Claim 2
Dependent Claim
238 words
A lateral DMOS transistor comprising a semiconductor substrate of a first conductivity type, a layer-shaped region on a first major surface of said substrate and forming a pn-junction with said substrate, a first surface-adjoining channel region of said first conductivity type in said layer-shaped region, a surface-adjoining source region of a second conductivity type opposite to that of the first in said channel region, a first surface-adjoining drain contact region of said second conductivity type in said layer-shaped region and spaced apart from said first channel region, an insulating layer on the surface of said transistor and covering at least that portion of the first surface-adjoining channel region located between said source region and said layer-shaped region, a first gate electrode on said insulating layer over at least said portion of the first channel region, and source-and first drain electrodes connected respectively to the source-and first drain contact regions, characterized in that said layer-shaped region is composed of a first semiconductor layer of said second conductivity type on said substrate, a second semiconductor layer of said first conductivity type on said first layer and a third surface-adjoining semiconductor layer of said second conductivity type on said second layer, in that said first surface-adjoining channel region is connected to said second layer, and in that an extended drain region is formed from a portion of said third layer between said first drain contact region and said first channel region.
Claim 3
Dependent Claim
63 words
A lateral DMOS transistor as in Claim 1, herein the doping level of said second layer is higher than that of said substrate, the doping level of said first channel region is higher than that of said second layer, and the doping level of said source and first drain contact regions is higher than the doping level of said first and third layers.
Claim 4
Dependent Claim
40 words
A lateral DMOS transistor as in Claim 2, wherein said source electrode electrically connects said source and first channel regions together, and further comprising a substrate electrode on a second =ajor surface of said substrate opposite said first major surface.
Claim 5
Dependent Claim
62 words
A lateral DMOS transistor as in Claim 1, further comprising a plurality of spaced-apart semiconductor zones of said second conductivity type located in that portion of said second semiconductor layer extending laterally from adjacent said first channel region to beneath said first drain contact region, said semiconductor zones ex- . tending vertically from said first semiconductor layer to said third semiconductor layer.
Claim 6
Dependent Claim
32 words
A lateral DMOS transistor as claimed in Claim 4, wherein said spaced-apart zones comprise strip-shaped zones extending con- tinucusly. from adjacent said first channel region to beneath said first drain contact region.
Claim 7
Dependent Claim
43 words
A lateral DMOS transistor as claimed in Claim 4, wherein each of said spaced-apart zones comprises a first subzone located adjacent said first channel region and a second subzone, spaced apart from said first subzone and located beneath said first drain contact region.
Claim 8
Dependent Claim
28 words
A lateral DMOS transistor as claimed in Claim 4, wherein said spaced-apart semiconductor zones comprise n-type zones having a doping level of about 10 16 donors/cm 3 .
Claim 9
Dependent Claim
137 words
A lateral DMOS transistor as in Claim 1, further comprising a second surface-adjoining drain end region of said first conductivity type in said third layer, extending down to said first layer, and electrically isolated from said first drain contact region by a p-n junction, a second surface-adjoining channel region of said second conductivity type between said first drain contact region and said second drain end region, said insulating layer on the surface of said transistor further covering that portion of the second surface-adjoining channel region located between said drain regions, a further surface-adjoining source region of said first conductivity type in said second surface-adjoining channel region and connected to said first drain electrode, and a further gate electrode on said insulating layer, over said portion of the second channel region and electrically isolated from said third layer.
Claim 10
Dependent Claim
62 words
A lateral DMOS transistor as in Claim 8, further comprising a plurality of spaced-apart semiconductor zones of said second conductivity type located in that portion of said second semiconductor layer extending laterally from adjacent said first channel region to at least beneath said first drain contact region, said semiconductor zones extending vertically from said first semiconductor layer to said third semiconductor layer.
Claim 11
Dependent Claim
33 words
A lateral DMOS transistor as claimed in Claim 9, wherein said spaced-apart zones comprise strip-shaped zones extending continuously from adjacent said first channel region to at least beneath said first drain contact region.
Claim 12
Dependent Claim
43 words
A lateral DMOS transistor as claimed in Claim 9, wherein each of said spaced-apart zones comprises a first subzcne located adjacent said first channel region and a second subzcne, spaced apart from said first subzone and located beneath said first drain contact region.
Claim 13
Dependent Claim
61 words
A lateral DMOS transistor as in Claim 1, wherein said first and third semiconductor layers comprise n-type layers having a doping level of about 10 16 donors/cm 3 and a thickness of about 2 microns, and said second semiconductor layer comprises a p-type layer having a doping level of about 10 16 acceptors/cm 3 and a thickness of about 2 microns.
References Cited (Backward Citations)
US3988761A
Cited
FR2458907A1
Cited
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