Insulated gate transistor with vertical integral diode and method of fabrication

Claim 1

A lateral insulated gate semiconductor device including: a body of semiconductor material comprising: a substrate of one type conductivity having a first surface which comprises a first major surface of said body, a first layer of opposite type conductivity disposed on an opposed major surface of said substrate; a first region of said one type conductivity disposed within said first layer and comprising a first portion of a second, opposed major surface of said body and forming a first PN junction with said first layer, a second region of said opposite type conductivity disposed within said first layer, comprising a second portion of said second surface of said body, being more heavily doped to said opposite conductivity type than said first layer and, at said second surface of said body, being surrounded by said first region, a third region of said one type conductivity disposed within said first layer, spaced from said first region and comprising a third portion of said second surface of said body, a fourth region of said opposite type conductivity disposed within said third region and comprising a fourth portion of said second surface of said body and forming a second PN junction with said third region, said first layer comprising a fifth portion of said second surface, said first region including laterally extending appendages which extend toward said third region, said second region being spaced from said first region appendages, said third region including laterally extending appendages which extend toward said first region and are interdigitated with said first region appendages; each of said first region appendages having a length L and a width W, such that the ratio of L to W is sufficient to effect a voltage drop in excess of 0.7 volts between said each appendage and an adjacent portion of said first layer in response to an on-state gate voltage and an anode-to-cathode voltage in the vicinity of and greater than 0.7 volts; a first cathode electrode disposed in ohmic contact with said substrate on said first surface thereof; an insulated gate disposed atop said second surface of said body above a portion of said third region and responsive to an appropriate bias for establishing a channel through said third region for coupling opposite type conductivity carriers from said fourth region through said third region to said first layer; a second cathode electrode disposed in ohmic contact with said third and fourth regions and shorting said third region to said fourth region to inhibit forward biasing of said second PN junction; an anode electrode disposed in ohmic contact with said first and second regions; and means connecting said second cathode electrode to said first cathode electrode so as to permit current flow through a vertical diode comprising said substrate, said first layer and said second region in response to the application of a bias potential across said first cathode electrode and said anode electrode in a polarity to forward bias said diode.