US5371047A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip interconnection having a breathable etch stop layer
Assignee: International Business Machines Corp
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Filing: 1992-10-30
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Granted: 1994-12-06
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Expires: 2012-10-30
Abstract
Abstract An integrated circuit having organic dielectric between interconnection layers eliminates damage caused by vapors outgassing from the organic dielectric by the use of a two-component organic layer having a breathable etch resistant organic layer above the main organic dielectric layer, both of the organic layers remaining in the final circuit. The etch resistant layer is resistant to the etchant used to pattern the layer of interconnect above the organic dielectric.
Inventors
- 👤 Stephen E. Greco
- 👤 Kris V. Srikrishnan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:23
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/47; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/093; H10W20/096; H10W20/40; H10W20/45; H10W20/48; Y; Y10; Y10S; Y10S148/00; Y10S148/043
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
355 words
A process of forming a reliable chip interconnection structure with at least two wiring levels having organic insulator and a permeable etch stop layer, comprising the steps of: a) providing an integrated circuit on semiconductor with a plurality of devices, said devices being covered with a layer of inorganic insulator, having a first surface and containing therein a plurality of first apertures and a first set of conductors passing over and making contacts to said devices through said first apertures; b) coating said first surface with a first organic layer, having a first organic layer thickness, and a first etch stop layer, having a first etch stop layer thickness less than said first organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a first composite dielectric layer; c) patterning a plurality of second apertures in said etch stop layer and said first organic layer; d) patterning a second conductor over said first etch stop layer to form a second set of conductors connecting said first set of conductors through said second apertures; e) coating said second set of conductors with a second organic layer, having a second organic layer thickness, and a second etch stop layer, having a second etch stop layer thickness less than said second organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a second composite dielectric layer; f) patterning a plurality of third apertures in said second organic layer and second etch stop layer, stopping on said first etch stop layer; and g) patterning a third conductor over said second etch stop layer, said conductor contacting said second conductor through said third apertures; and repeating said steps b) to g) at least once; in which at least one of said first and second etch stop layers is formed subsequent to the formation of an inorganic etch stop layer over one of said first and second organic layers to protect said one of said first and second organic layers from a reactive ion etching step, followed by removal of said inorganic etch stop layer.
Claim 2
Dependent Claim
355 words
A process of forming a reliable chip interconnection structure with at least two wiring levels having organic insulator and a permeable etch stop layer, comprising the steps of: a) providing an integrated circuit on semiconductor with a plurality of devices, said devices being covered with a layer of inorganic insulator, having a first surface and containing therein a plurality of first apertures and a first set of conductors passing over and making contacts to said devices through said first apertures; b) coating said first surface with a first organic layer, having a first organic layer thickness, and a first etch stop layer, having a first etch stop layer thickness less than said first organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a first composite dielectric layer; c) patterning a plurality of second apertures in said etch stop layer and said first organic layer; d) patterning a second conductor over said first etch stop layer to form a second set of conductors connecting said first set of conductors through said second apertures; e) coating said second set of conductors with a second organic layer, having a second organic layer thickness, and a second etch stop layer, having a second etch stop layer thickness less than said second organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a second composite dielectric layer; f) patterning a plurality of third apertures in said second organic layer and second etch stop layer, stopping on said first etch stop layer; and g) patterning a third conductor over said second etch stop layer, said conductor contacting said second conductor through said third apertures; and repeating said steps b) to g) at least once; in which at least one of said first and second etch stop layers is formed subsequent to the formation of an inorganic etch stop layer over one of said first and second organic layers to protect said one of said first and second organic layers from a reactive ion etching step, followed by removal of said inorganic etch stop layer.
Claim 3
Dependent Claim
353 words
A process of forming a reliable chip interconnection structure with at least two wiring levels having an organic insulator and a permeable etch stop layer, comprising the steps of: a) providing an integrated circuit on semiconductor with a plurality of devices, said devices being covered with a layer of inorganic insulator, having a first surface and containing therein a plurality of first apertures and a first set of conductors passing over and making contacts to said devices through said first apertures; b) coating said first surface with a first organic layer, having a first organic layer thickness, and a first etch stop layer, having a first etch stop layer thickness less than said first organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a first composite dielectric layer; c) patterning a plurality of second apertures in said etch stop layer and said first organic layer; d) patterning a second conductor over said first etch stop layer to form a second set of conductors contacting said first set of conductors through said second apertures; e) coating said second set of conductors with a second organic layer, having a second organic layer thickness, and a second etch stop layer, having a second etch stop layer thickness less than said second organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a second composite dielectric layer; f) patterning a plurality of third apertures in said second organic layer and second etch stop layer, stopping on said first etch stop layer; and g) patterning a third conductor over said second etch stop layer, said conductor contacting said second conductor through said third apertures; and repeating said steps b) to g) at least once; in which at least one of said first and second etch stop layers is formed subsequent to the use of an inorganic etch stop over one of said first and second organic layers to protect said one of said first and second organic layers from a metal polishing process, followed by removal of said inorganic etch stop.
Claim 4
Dependent Claim
353 words
A process of forming a reliable chip interconnection structure with at least two wiring levels having an organic insulator and a permeable etch stop layer, comprising the steps of: a) providing an integrated circuit on semiconductor with a plurality of devices, said devices being covered with a layer of inorganic insulator, having a first surface and containing therein a plurality of first apertures and a first set of conductors passing over and making contacts to said devices through said first apertures; b) coating said first surface with a first organic layer, having a first organic layer thickness, and a first etch stop layer, having a first etch stop layer thickness less than said first organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a first composite dielectric layer; c) patterning a plurality of second apertures in said etch stop layer and said first organic layer; d) patterning a second conductor over said first etch stop layer to form a second set of conductors contacting said first set of conductors through said second apertures; e) coating said second set of conductors with a second organic layer, having a second organic layer thickness, and a second etch stop layer, having a second etch stop layer thickness less than said second organic layer thickness, permeable to outgassing vapors from said organic layer underneath in subsequent process steps, thereby forming a second composite dielectric layer; f) patterning a plurality of third apertures in said second organic layer and second etch stop layer, stopping on said first etch stop layer; and g) patterning a third conductor over said second etch stop layer, said conductor contacting said second conductor through said third apertures; and repeating said steps b) to g) at least once; in which at least one of said first and second etch stop layers is formed subsequent to the use of an inorganic etch stop over one of said first and second organic layers to protect said one of said first and second organic layers from a metal polishing process, followed by removal of said inorganic etch stop.
Claim 5
Dependent Claim
29 words
A process according to claim 1, in which at least one of said first and second etch stop layers comprise organic insulators co-polymerized with a silicon containing organic compound.
Claim 6
Dependent Claim
29 words
A process according to claim 2, in which at least one of said first and second etch stop layers comprise organic insulators co-polymerized with a silicon containing organic compound.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |