Method for forming interconnects

Claim 2

A process for forming at least one additional level of metal interconnect to contact a lower level of metal in a semiconductor device, comprising: (a) forming said lower level of metal and patterning said metal to form isolated contact areas; (b) filling regions between said isolated contact areas with a dielectric material and planariz­ing the resulting structure to the top surface of said isolated contact areas; (c) forming a first dielectric layer on said planarized layer; (d) forming a second dielectric layer on said first dielectric layer; (e) etching contact holes through both said dielectric layers in a two-step process that comprises etching said second dielectric layer with an etchant that selectively etches said second dielectric layer relative to said first dielectric layer to expose por­tions of said first dielectric layer and then etching said first dielectric layer with an etchant that selec­tively etches said first dielectric layer relative to said dielectric material isolating said lower level metal contact areas to expose at least a portion of said lower level metal contact areas; and (f) forming said at least one additional level of metal interconnect over said second dielectric layer and into said contact holes to contact said lower level metal contact area.

Claim 3

The process of Claim 1 wherein said first di­electric layer consists essentially of silicon nitride.

Claim 4

The process of Claim 1 wherein said second dielectric layer consists essentially of silicon dioxide.

Claim 5

A process for forming at least one additional level of metal interconnect to contact a lower level of metal in a silicon semiconductor device, comprising: (a) forming said lower level of metal and patterning said metal to form isolated contact areas; (b) filling regions between said isolated contact areas with silicon dioxide and planarizing the resulting structure to the top surface of said isolated contact areas; (c) forming a first dielectric layer consisting essentially of silicon nitride on said planarized layer; (d) forming a second dielectric layer consisting essentially of silicon dioxide on said first dielectric layer; (e) etching contact holes through both said dielectric layers in a two-step process that comprises etching said second dielectric layer with an etchant that selectively etches said second dielectric layer relative to said first dielectric layer to expose portions of said first dielectric layer and then etching said first dielectric layer with an etchant that selectively etches said first dielectric layer relative to said dielectric material isolating said lower level metal contacts to expose at least a portion of said lower level metal contacts; and (f) forming said at least one additional level of metal interconnect over said second dielectric layer and into said contact holes to contact said lowe level metal contact area.

Claim 6

A process for forming at least one additional level of metal interconnect to contact a lower level of metal in a silicon semiconductor device, comprising: (a) forming said lower level of metal and patterning said metal to form isolated contact areas; (b) filling regions between said isolated contact areas with silicon dioxide and planarizing the resulting structure to the top surface of said isolated contact areas; (c) forming a first dielectric layer consisting essentially of silicon nitride on said planarized layer; (d) forming a second dielectric layer consisting essentially of silicon dioxide on said first dielectric layer; (e) etching contact holes through both said dielectric layers in a two-step process that comprises etching said second dielectric layer with an etchant that selectively etches said second dielectric layer relative to said first dielectric layer to expose portions of said first dielectric layer and then etching said first dielectric layer with an etchant that selectively etches said first dielectric layer relative to said dielectric material isolating said lower level metal contacts to expose at least a portion of said lower level metal contacts; and (f) forming said at least one additional level of metal interconnect over said second dielectric layer and into said contact holes to contact said lowe level metal contact area.

Claim 7

The process of Claim 1 or 3 wheren additional levels of metal interconnects are formed to lower level metal layers employing the formation of said two dielectric layers and said two-step etching process to form said contact holes.

Claim 8

The process of Claim 1 or 3 wherein said dielectric material comprises at least one layer of silicon dioxide.

Claim 9

The process of Claim 2 or 4 wherein said silicon nitride layer is formed to a thickness ranging from about 400 to 800 A.

Claim 10

The process of Claim 3 or 4 wherein said silicon dioxide layer is formed to a thickness ranging from about 6,000 to 8,000 A.

Claim 11

A structure comprising at least two metal interconnect layers (14,20) separated vertically from each other by two dielectric layers (28,30), a first etch-stop layer (28) formed on a lower metal layer (14) and a second layer (30) formed on said first layer, with an upper metal layer (20) formed on said second layer, with contact holes (10) between each metal layer filled with metal (20a) of said upper layer and contacting metal of said lower layer.

Claim 12

A structure comprising at least two metal interconnect layers (14,20) separated vertically from each other by two dielectric layers (28,30), a first etch-stop layer (28) formed on a lower metal layer (14) and a second layer (30) formed on said first layer, with an upper metal layer (20) formed on said second layer, with contact holes (10) between each metal layer filled with metal (20a) of said upper layer and contacting metal of said lower layer.

Claim 13

The structure of Claim 9 wherein said first dielectric layer consists essentially of silicon nitride.

Claim 14

The structure of Claim 9 wherein said second dielectric layer consists essentially of silicon dioxide.

Claim 15

A structure comprising at least two metal interconnect layers (14,20) separated vertically from each other by two dielectric layers (28,30), a first etch-stop layer (28) consisting essentially of silicon nitride formed on a lower metal layer (14) and a second layer (30) consisting essentially of silicon dioxide formed on said first layer, with an upper metal layer (20) formed on said second layer, with contact holes (10) between each metal layer filled with metal (20a) of said upper layer and contacting metal of said lower layer.

Claim 16

A structure comprising at least two metal interconnect layers (14,20) separated vertically from each other by two dielectric layers (28,30), a first etch-stop layer (28) consisting essentially of silicon nitride formed on a lower metal layer (14) and a second layer (30) consisting essentially of silicon dioxide formed on said first layer, with an upper metal layer (20) formed on said second layer, with contact holes (10) between each metal layer filled with metal (20a) of said upper layer and contacting metal of said lower layer.

Claim 17

The structure of Claim 9 or 12 comprising additional metal interconnect layers (20′), each layer separated vertically from the other by said two dielectric layers (28′, 30′), with contact holes between each metal layer filled with metal of an upper layer and contacting metal of a lower layer.

Claim 18

The structure of Claim 13 wherein each said lower layer comprises patterned metal contact areas, with regions between said metal contact areas filled with a dielectric material (24,26).

Claim 19

The structure of claim 14 wherein said dielectric material comprises at least one layer of silicon dioxide.

Claim 20

The structure of claim 10 or 12 wherein said silicon nitride layer has a thickness ranging from about 400 to 800 A.

Claim 21

The structure of Claim 11 or 16 wherein said silicon dioxide layer has a thickness ranging from about 6,000 to 8,000 A.