EP0154419A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process for producing an interconnection structure of a semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1985-02-08
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Granted: —
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Expires: 2005-02-08
Abstract
Abstract Planarization of an insulating layer (10) formed on a lower wiring layer (8-6, 8-4, 8-2) and having steps at the shoulders of the wiring patterns, can be attained. On a lower wiring layer (8-6, 8-4, 8-2), a lower insulating layer (10) is formed and a heat resistive material (16) is coated over the lower insulating layer, to form a substantially planar top surface and to fill cavities (22) appearing in the surface of the , lower insulating layer with material (16). Then, etching is carried out to preserve the profile of the surface of the coating layer (16) and to remove the coating layer at portions (18) where through-holes (26) are to be formed. The cavities (22) are still filled with the material (16) after etching. An upper insulating layer (24) is deposited on the exposed lower insulating layer (10) and the remaining part of the coating layer (16). Through-holes (26) and an upper wiring layer (28) are formed. Thus, the upper wiring layer (28) has no contact with the remaining part of the coating layer (16) and the remaining part of the coating layer is never externally exposed.
Inventors
- 👤 Takahiro Tuchiya
- 👤 Kazuaki Room 2501 Fujitsu-Aobasai-Ryo Tukuda
- 👤 Tadakazu Takada
- 👤 Hiroshi Goto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 05:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/47; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W20/01; H10W20/071; H10W20/092; H10W20/48
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
209 words
A process for fabricating a semiconductor device, comprising the steps of: forming a lower wiring layer of given patterns on a substrate; forming a lower insulating layer on the lower wiring layer and the substrate; forming a coating layer of a heat resisting material on the lower insulating layer by coating, thereby filling cavities appearing in the top surface of the lower insulating layer with the heat resisting material and giving a substantially planular top surface to the coating layer; etching the entire surface of the coating layer until a portion of the coating layer on at least a part of the lower wiring layer is completely removed, whereby the cavities remaining after the etching remain filled with the heat resisting material, and the resultant top surface after the etching is substantially planular; forming an upper insulating layer on the lower insulating layer and the remaining heat resisting material; forming through-holes passing through the upper and lower insulating layers and reaching the lower wiring layer where the heat resisting material is completely removed by the etching; and forming an upper wiring layer of given patterns on the upper insulating layer and in the through-holes, the upper wiring layer being electrically connected with the lower wiring layer through the through-holes.
Claim 2
Dependent Claim
209 words
A process for fabricating a semiconductor device, comprising the steps of: forming a lower wiring layer of given patterns on a substrate; forming a lower insulating layer on the lower wiring layer and the substrate; forming a coating layer of a heat resisting material on the lower insulating layer by coating, thereby filling cavities appearing in the top surface of the lower insulating layer with the heat resisting material and giving a substantially planular top surface to the coating layer; etching the entire surface of the coating layer until a portion of the coating layer on at least a part of the lower wiring layer is completely removed, whereby the cavities remaining after the etching remain filled with the heat resisting material, and the resultant top surface after the etching is substantially planular; forming an upper insulating layer on the lower insulating layer and the remaining heat resisting material; forming through-holes passing through the upper and lower insulating layers and reaching the lower wiring layer where the heat resisting material is completely removed by the etching; and forming an upper wiring layer of given patterns on the upper insulating layer and in the through-holes, the upper wiring layer being electrically connected with the lower wiring layer through the through-holes.
Claim 3
Dependent Claim
27 words
A process according to claim 1, wherein the lower and upper insulating layers are made of silicon dioxide, phosphosilicate glass (PSG), silicon nitride, or silicon nitride oxide.
Claim 4
Dependent Claim
27 words
A process according to claim 1 or 2, wherein the lower and upper insulating layers are formed by CVD, plasma CVD, sputtering, bias sputtering, or ion plating.
Claim 5
Dependent Claim
31 words
A process according to claim 1, 2 or 3 wherein the heat resisting material is a silicone system resin, a polyimide system resin, a photosensitive polyimide, or a heat resisting resist.
Claim 6
Dependent Claim
19 words
A process according to claim 1, 2, 3 or 4 wherein the coating layer is formed by spin coating.
Claim 7
Dependent Claim
53 words
A process according to any of claims 1 to 5, wherein the coating layer of a heat resisting material is made by coating a starting material on the lower wiring layer and the exposed substrate and heating the resultant layer of the starting material to cause it to change into a final material.
Claim 8
Dependent Claim
24 words
A process according to claim 6, wherein the starting material is a silicon system resin and the final material is a silicon dioxide-like material.
Claim 9
Dependent Claim
42 words
A process according to claim 6 or 7, wherein the step of heating for changing the starting material to the final material is effected before the step of etching the coating layer and, if necessary, a part of the lower insulating layer.
Claim 10
Dependent Claim
51 words
A process according to claim 6 or 7, wherein the step of heating for changing the starting material to the final material is effected after the step of etching the coating layer and, if necessary, a part of the lower insulating layer, before the step of forming the upper insulating layer.
Claim 11
Dependent Claim
40 words
A process according toany preceding claim , wherein the etching of the coating layer and a part of the lower insulating layer is carried out with substantially the same etching rates for the coating layer and the lower insulating layer.
Claim 12
Dependent Claim
21 words
A process according to any preceding claim , wherein the etching is effected by controlled etching, ion milling, or plasma etching.
Claim 13
Dependent Claim
35 words
A process according to any preceding claim , wherein the substrate includes a further wiring layer below the lower wiring layer with an insulating layer between the further wiring layer and the lower wiring layer.
Claim 14
Dependent Claim
33 words
A process according to claim 12, wherein the insulating layer to be formed between the further wiring layer and the lower insulating layer is itself made by a process according to claim 1.
Claim 15
Dependent Claim
45 words
A process according to any preceding claim , wherein the lower insulating layer is formed on the lower wiring layer and the exposed substrate in a thickness less than the half of the least space between adjacent patterns of the lower wiring layer. preceding claim
Claim 16
Dependent Claim
22 words
A process according to any / , wherein the lower wiring layer of given patterns has patterns of different widths. preceding claim
Claim 17
Dependent Claim
17 words
A process according to any / , wherein the lower wiring layer is of metal or poly-silicon.
Claim 18
Dependent Claim
17 words
A process according to any / , wherein the lower wiring layer is of metal or poly-silicon.
Claim 19
Dependent Claim
20 words
preceding claim 17. A process according to any / , wherein the upper wiring layer is of metal or poly-silicon.
References Cited (Backward Citations)
No citation records indexed.
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