US5367655A
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Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells
Assignee: Motorola Solutions Inc
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Filing: 1991-12-23
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Granted: 1994-11-22
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Expires: 2011-12-23
Abstract
Abstract A memory (10) that has a shorter access time and higher reliability in a special mode of operation. In one form, the memory (10) has a special mode of operation in which multiple memory rows are simultaneously selected. As a consequence, multiple memory cells (44) are used to drive each bit line pair. Using multiple memory cells (44) to drive each bit line pair allows the bit lines to be driven to the proper logic state in a shorter time. This speeds up accesses to memory (10). Using multiple memory cells (44) to drive each bit line pair also improves the reliability of memory (10). Because multiple memory cells (44) are used to drive the same bit line pair, a failure of one memory cell (44) still leaves one or more functioning memory cells (44) to drive the correct logic state on the bit line pair. The memory may be incorporated in a cache controller of a data processing system in which only a part of the memory is being used. The extra unneeded memory cells may be used to help drive the bit lines to allow the cache controller to execute operations more quickly.
Inventors
- 👤 Anita S. Grossman
- 👤 Paul A. Reed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0895; G11; G11C; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
184 words
A memory circuit, comprising: a control conductor for transferring a control signal; a plurality of memory cells, including a first memory cell located in a first row and a first column, and including a second memory cell located in a second row and the first column; a bit line; and select logic means for receiving the control signal, and in response to the control signal having a first logic state, said select logic means coupling the first memory cell to said bit line so that the memory circuit is accessed in a first access time, and in response to the control signal having a second logic state, said select logic means coupling both the first memory cell and the second memory cell to said bit line so that the memory circuit is accessed in a second access time, the second access time being of shorter duration than the first access time, said select logic means being coupled to said control conductor and to said plurality of memory cells wherein said plurality of memory cells is a plurality of static random access memory (SRAM) cells.
Claim 2
Dependent Claim
184 words
A memory circuit, comprising: a control conductor for transferring a control signal; a plurality of memory cells, including a first memory cell located in a first row and a first column, and including a second memory cell located in a second row and the first column; a bit line; and select logic means for receiving the control signal, and in response to the control signal having a first logic state, said select logic means coupling the first memory cell to said bit line so that the memory circuit is accessed in a first access time, and in response to the control signal having a second logic state, said select logic means coupling both the first memory cell and the second memory cell to said bit line so that the memory circuit is accessed in a second access time, the second access time being of shorter duration than the first access time, said select logic means being coupled to said control conductor and to said plurality of memory cells wherein said plurality of memory cells is a plurality of static random access memory (SRAM) cells.
Claim 3
Dependent Claim
17 words
A memory circuit as in claim 1, further comprising: a data bus coupled to said bit line.
Claim 4
Dependent Claim
41 words
A memory circuit as in claim 1, further comprising: column select logic, coupled to said plurality of memory cells; a plurality of address conductors, coupled to said column select logic; and cache control circuitry, coupled to said plurality of address conductors.
Claim 5
Dependent Claim
54 words
A memory circuit as in claim 1, wherein the memory circuit further comprises: an address bus for receiving a plurality of address signals from external to the memory circuit, said address bus being coupled to said select logic means; and wherein said select logic means receives a portion of the plurality of address signals.
Claim 6
Dependent Claim
110 words
A memory circuit as in claim 4, wherein said plurality of memory cells further includes: a third memory cell located in a third row and the first column; and a fourth memory cell located in a fourth row and the first column; and wherein in response to the control signal having the second logic state and the portion of the plurality of address signals having a predetermined value, said select logic means couples the first, second, third, and fourth memory cells to said bit line so that the memory circuit is accessed in a third access time, the third access time being of shorter duration than the second access time.
Claim 7
Dependent Claim
29 words
A memory circuit as in claim 1, further comprising: control means for providing the control signal to said control conductor, said control means being coupled to said control conductor.
Claim 8
Dependent Claim
17 words
A memory circuit as in claim 6, wherein said control means comprises: a user programmable register circuit.
Claim 9
Dependent Claim
16 words
A memory circuit as in claim 6, wherein said control means comprises: an integrated circuit pin.
Claim 10
Independent Claim
200 words
A method for operating a memory, the memory being a static random access memory (SRAM), the memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, the method comprising the steps of: selecting one of a slower operating mode and a faster operating mode, the slower operating mode having a first memory access time and the faster operating mode having a second memory access time, the second memory access time having a shorter time duration than the first memory access time; receiving an address; if the slower operating mode is selected, selecting a first one of the plurality of rows and one of the plurality of columns corresponding to the address; if the slower operating mode is selected, accessing the memory with the first memory access time to retrieve a stored information value; if the faster operating mode is selected, selecting the first one of the plurality of rows, a second one of the plurality of rows, and the one of the plurality of columns corresponding to the address; and if the faster operating mode is selected, accessing the memory with a second memory access time to retrieve the stored information value.
Claim 11
Independent Claim
200 words
A method for operating a memory, the memory being a static random access memory (SRAM), the memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, the method comprising the steps of: selecting one of a slower operating mode and a faster operating mode, the slower operating mode having a first memory access time and the faster operating mode having a second memory access time, the second memory access time having a shorter time duration than the first memory access time; receiving an address; if the slower operating mode is selected, selecting a first one of the plurality of rows and one of the plurality of columns corresponding to the address; if the slower operating mode is selected, accessing the memory with the first memory access time to retrieve a stored information value; if the faster operating mode is selected, selecting the first one of the plurality of rows, a second one of the plurality of rows, and the one of the plurality of columns corresponding to the address; and if the faster operating mode is selected, accessing the memory with a second memory access time to retrieve the stored information value.
Claim 12
Dependent Claim
92 words
A method as in claim 9, further comprising the steps of: if the slower operating mode is selected, coupling a bit line to a first portion of memory cells located in the first one of the plurality of rows and the one of the plurality of columns; and if the faster operating mode is selected, coupling the bit line to the first portion of memory cells and to a second portion of memory cells located in the second one of the plurality of rows and the one of the plurality of columns.
Claim 13
Dependent Claim
32 words
A method as in claim 9, wherein said step of selecting one of the slower operating mode and the faster operating mode comprises the steps of: programming at least one register bit.
Claim 14
Dependent Claim
35 words
A method as in claim 9, wherein said step of selecting one of the slower operating mode and the faster operating mode comprise the step of: receiving a control signal at an integrated circuit pin.
Claim 15
Dependent Claim
27 words
A method as in claim 9, further comprising the steps of: receiving an input information value; and comparing the stored information value to the input information value.
Claim 16
Dependent Claim
46 words
A method as in claim 13, further comprising the step of: providing a hit signal in response to said step of comparing the stored information value to the input information value, the hit signal being asserted if the stored information value matches the input information value.
Claim 17
Dependent Claim
18 words
A method as in claim 13, further comprising the step of: determining if a cache hit has occurred.
Claim 18
Dependent Claim
36 words
A method as in claim 15, wherein the memory is a cache tag memory, the comprising the step of: providing a plurality of control signals to a cache memory array if the cache hit has occurred.
Claim 19
Independent Claim
238 words
A method for operating a static random access (SRAM) memory in a cache controller, the memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, the method comprising the steps of: selecting one of a slower operating mode and a faster operating mode, the slower operating mode having a first memory access time and the faster operating mode having a second memory access time, the second memory access time having a shorter time duration than the first memory access time; receiving an address from a processor; if the slower operating mode is selected, selecting a first one of the plurality of rows and one of the plurality of columns corresponding to the address; if the slower operating mode is selected, accessing the memory with the first memory access time to retrieve a stored information value; if the faster operating mode is selected, selecting the first one of the plurality of rows, a second one of the plurality of rows, and the one of the plurality of columns corresponding to the address; if the faster operating mode is selected, accessing the memory with a second memory access time to retrieve the stored information value; comparing the stored information value to a first value received from the processor to determine if a cache hit has occurred; and if the cache hit has occurred, providing a plurality of control signals to a cache.
Claim 20
Independent Claim
238 words
A method for operating a static random access (SRAM) memory in a cache controller, the memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, the method comprising the steps of: selecting one of a slower operating mode and a faster operating mode, the slower operating mode having a first memory access time and the faster operating mode having a second memory access time, the second memory access time having a shorter time duration than the first memory access time; receiving an address from a processor; if the slower operating mode is selected, selecting a first one of the plurality of rows and one of the plurality of columns corresponding to the address; if the slower operating mode is selected, accessing the memory with the first memory access time to retrieve a stored information value; if the faster operating mode is selected, selecting the first one of the plurality of rows, a second one of the plurality of rows, and the one of the plurality of columns corresponding to the address; if the faster operating mode is selected, accessing the memory with a second memory access time to retrieve the stored information value; comparing the stored information value to a first value received from the processor to determine if a cache hit has occurred; and if the cache hit has occurred, providing a plurality of control signals to a cache.
Claim 21
Dependent Claim
21 words
A method as in claim 17, further comprising the step of: writing the stored information value into multiple memory locations simultaneously.
Claim 22
Dependent Claim
18 words
A method as in claim 18, wherein said step of writing is performed during testing of the memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |