US4954994A
Expired / Lapsed
US
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FIFO memory capable of simultaneously selecting a plurality of word lines
Assignee: Texas Instruments Inc
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Filing: 1988-09-16
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Granted: 1990-09-04
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Expires: 2008-09-16
Abstract
Abstract A semiconductor memory device is constructed so that a plurality of word lines may be simultaneously selected by the transfer of information through a plurality of shift register positions of a shift register, wherein the respective shift register positions are connected to individual word lines. Simultaneously with the selection of the word lines, data may be written in or readout from the memory. The shift register is part of an address decoder which also includes logic circuits providing first and second selector devices. The first selector device is connected between a control circuit and the initial shift register position, while the second selector device is connected between the control circuit and each of the plurality of shift register positions arranged in parallel. When the first selector device is activated by a first control signal from the control circuit, binary data is clocked through each of the shift register positions. Then, a second control signal activates the second selector device for producing an output signal to each of the shift register positions, thereby applying the information thereof to the word lines and simultaneously selecting those word lines corresponding to shift register positions in which a logic "1" has been stored.
Inventors
- 👤 Masahi Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:39
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C8/04; G06; G06F; G06F5/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
321 words
A semiconductor memory device comprising: a plurality of word lines; a readout line buffer; an output buffer connected to said readout line buffer for receiving the output therefrom; control circuit means including a data write-in row address counter and having a plurality of outputs, one of which is connected to each of said plurality of word lines; at least one address decoder including shift register having a plurality of successive shift register positions respectively connected to corresponding individual word lines, first selector means connected between one of the outputs of said control circuit means and the initial shift register position of said shift register for receiving a first control signal from said control circuit means, and second selector means connected between another output of said control circuit and each of the plurality of shift register positions arranged in parallel for receiving a second control signal from said control circuit means; binary data as applied to said shift register being successively shifted through each of said plurality of shift register positions in response to said first control signal activating said first selector means to provide a series of output signals as binary data in one of two binary logic states for storage in the initial shift register position and in each of the remaining shift register positions; one of the two binary logic states if stored in a respective shift register position designating the selection of the word line corresponding thereto, and the other of the two binary logic states if stored in a respective shift register position designating the non-selection of the word line corresponding thereto; and each of shift pluality of word lines corresponding to a respective shift register position having said one binary logic state stored therein being selected so as to be conductive in response to said second control signal activating said second selector means to provide an output signal to each of said shift register positions simultaneously.
Claim 2
Dependent Claim
321 words
A semiconductor memory device comprising: a plurality of word lines; a readout line buffer; an output buffer connected to said readout line buffer for receiving the output therefrom; control circuit means including a data write-in row address counter and having a plurality of outputs, one of which is connected to each of said plurality of word lines; at least one address decoder including shift register having a plurality of successive shift register positions respectively connected to corresponding individual word lines, first selector means connected between one of the outputs of said control circuit means and the initial shift register position of said shift register for receiving a first control signal from said control circuit means, and second selector means connected between another output of said control circuit and each of the plurality of shift register positions arranged in parallel for receiving a second control signal from said control circuit means; binary data as applied to said shift register being successively shifted through each of said plurality of shift register positions in response to said first control signal activating said first selector means to provide a series of output signals as binary data in one of two binary logic states for storage in the initial shift register position and in each of the remaining shift register positions; one of the two binary logic states if stored in a respective shift register position designating the selection of the word line corresponding thereto, and the other of the two binary logic states if stored in a respective shift register position designating the non-selection of the word line corresponding thereto; and each of shift pluality of word lines corresponding to a respective shift register position having said one binary logic state stored therein being selected so as to be conductive in response to said second control signal activating said second selector means to provide an output signal to each of said shift register positions simultaneously.
Claim 3
Dependent Claim
210 words
A semiconductor memory device as set forth in claim 1, further including a data output terminal connected to the output of said output buffer and to an input of said first selector means; a test signal terminal connected to one input of said first selector means and to one input of said output buffer, said test signal terminal being adapted to receive a binary test signal in one of two binary logic states; a binary test signal from said test signal terminal at one of the two binary logic states activating said output buffer to enable the output from said readout line buffer to be provided to said data output terminal via said output buffer; a binary test signal from said test signal terminal at the other of the two binary logic states deactivating said output buffer to disconnect said readout line buffer from said data output terminal; and the binary data as applied to said shift register in response to said first control signal activating said first selector means being initially input to said data output terminal for transmission to said input of said first selector means connected thereto when the binary test signal from said test signal terminal is at the other of the two binary logic states.
Claim 4
Dependent Claim
73 words
A semiconductor memory device as set forth in claim 2, wherein said memory device is capable of FIFO operation, and includes a write-in cycle control terminal; said address decoder comprising a row decoder of said FIFO memory device, said first selector means being connected as part of said row decoder to said output buffer, and said second selector means being connected as part of said row decoder to said write-in cycle control terminal.
Claim 5
Dependent Claim
88 words
A semiconductor memory device as set forth in claim 2, wherein said control circuit means is effective to provide a third control signal at said one binary logic state on said one output connected to each of said plurality of word lines; each of said selected word lines receiving write-in data at said one binary logic state as provided by said third control signal such that preselected binary data patterns may be written into a memory array defined by a matrix of intersecting word lines and bit lines.
Claim 6
Dependent Claim
31 words
A semiconductor memory device as set forth in claim 4, wherein each of said selected word lines receives write-in data at said one binary logic state simultaneous to the selection thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |