Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
I. A semiconductor memory device for a data processing system having a main memory, a cache memory, and a central processor unit, said main memory comprising N memory sets, each of said memory sets being constituted by a plurality of memory blocks, said cache memory being adapted to store data of n memory sets where n is smaller than N, said memory device comprising: memory means for storing address data of upper address portions each of which designates a memory set of data stored in an address in said cache memory, said address data being stored in an address in said memory device corresponding to said address in said cache memory, both the addresses designating a memory block in said designated memory set, means for storing validity bits for indicating a validlinvalid state of address data in each address of said memory means, and an initialization circuit for invalidating all of said validity bits.
Claim 2
Independent Claim
27 words
A device according to claim I, wherein each section of a tag memory of a cache memory comprises a tag data portion and a validity bit portion.
Claim 3
Dependent Claim
32 words
A device according to claim 2, wherein said tag data portion comprises pairs of bit lines, word lines, memory cells, transfer gates for the memory cells, and source voltage supply control transistors.
Claim 4
Dependent Claim
20 words
A device according to claim 3, wherein one of said source voltage supply control transistors receives a control signal (PGi)
Claim 5
Dependent Claim
33 words
A device according to claim 2, wherein the validity bit portion comprises a pair of bit lines, word lines, memory cells, transfer gates for the memory cells, and source voltage supply control transistors.
Claim 6
Dependent Claim
22 words
A device according to claim 5, wherein one of said source voltage supply control circuits receives a control signal (PG 1 )
Claim 7
Dependent Claim
41 words
A device according to claim 4, wherein each of the word lines in the validity bit portion is connected with a series circuit of a NOR gate and an inverter, and the NOR gate receives a control signal (PG 2 )
Claim 8
Independent Claim
49 words
A device according to claim I, wherein a comparator is connected with each section of a tag memory for making an output signal (Si) HIGH when a result of a comparison between the data read from the tag data portion and the upper address portion indicates a coincidence therebetween.
Claim 9
Independent Claim
68 words
A device according to claim I, wherein a write buffer is connected with each section of a tag memory for writing information of an upper address portion into a designated lower address portion of the tag memory in response to a write signal, a writing of data "I" into the validity bit portion for the lower address portion being simultaneously carried out in correspondence with the write signal.
Claim 10
Independent Claim
65 words
A device according to claim I, wherein said initialization circuit comprises a word line selecting circuit for selecting all of the word lines of the memory device, and a validity bit invalidation circuit for preventing a supply of voltage to all bit lines of the tag data portion by a voltage source and writing data "0" into the memory cells of the validity bit portion.