Process for fabricating a MOS device having protection against electrostatic discharge

Claim 2

A process for fabricating a MOS device having protection against electrostatic discharge, comprising the steps of: providing a semiconductor substrate; growing an epitaxial layer on said semiconductor substrate; forming a tie-down region in said epitaxial layer; growing a layer of insulating material on said epitaxial layer for forming an insulating layer of an electrode of a MOS device; forming a buried protection diode window through said electrode insulating layer at a location directly above said tie-down region so as to expose said tie-down region; depositing a layer of conductive material over said electrode insulating layer for forming a conductive layer of said electrode of the MOS device, said layer of conductive material filling said buried protection diode window and forming a protection diode in said tie-down region; and etching said layer of conductive material and said layer of insulating material so as to form said electrode of the MOS device, said protection diode being formed directly below said electrode insulating layer such that said protection diode is formed integrally as part of the MOS device; wherein excess charge buildup in the MOS device is conducted through said electrode conductive layer and away from the MOS device by said protection diode.

Claim 3

A process for fabricating a MOS device according to claim 1, wherein said layer of insulating material comprises oxide.

Claim 4

A process for fabricating a MOS device according to claim 1, wherein said layer of insulating material comprises nitride.

Claim 5

A process for fabricating a MOS device according to claim 1, wherein said layer of insulating material comprises oxide and nitride.

Claim 6

A process for fabricating a MOS device according to claim 1, wherein said layer of conductive material comprises polysilicon.

Claim 7

A process for fabricating a MOS device according to claim 1, wherein said layer of conductive material comprises metal.

Claim 8

A process for fabricating a MOS device according to claim 1, wherein said layer of conductive material comprises single crystal silicon.

Claim 9

A process for fabricating a MOS transistor having protection against electrostatic discharge, comprising the steps of: providing a semiconductor substrate; growing an epitaxial layer on said semiconductor substrate; forming isolations in said epitaxial layer; forming a source region of a MOS transistor, a drain region of the MOS transistor and a tie-down region in said epitaxial layer between said isolations, said regions being defined by said isolations; growing a layer of insulating material on said epitaxial layer for forming a gate insulating layer of the MOS transistor; forming a buried protection diode window through said gate insulating layer at a location directly above said tie-down region so as to expose said tie-down region; depositing a layer of conductive material over said gate insulating layer for forming a gate conductive layer of the MOS transistor, said layer of conductive material filling said buried protection diode window and forming a protection diode in said tie-down region; and etching said layer of conductive material and said layer of insulating material so as to form a gate of the MOS transistor, said protection diode being formed directly below said gate insulating layer such that said protection diode is formed integrally as part of the MOS transistor; wherein excess charge buildup in the MOS transistor is conducted through said gate conductive layer and away from the MOS transistor by said protection diode.

Claim 10

A process for fabricating a MOS transistor having protection against electrostatic discharge, comprising the steps of: providing a semiconductor substrate; growing an epitaxial layer on said semiconductor substrate; forming isolations in said epitaxial layer; forming a source region of a MOS transistor, a drain region of the MOS transistor and a tie-down region in said epitaxial layer between said isolations, said regions being defined by said isolations; growing a layer of insulating material on said epitaxial layer for forming a gate insulating layer of the MOS transistor; forming a buried protection diode window through said gate insulating layer at a location directly above said tie-down region so as to expose said tie-down region; depositing a layer of conductive material over said gate insulating layer for forming a gate conductive layer of the MOS transistor, said layer of conductive material filling said buried protection diode window and forming a protection diode in said tie-down region; and etching said layer of conductive material and said layer of insulating material so as to form a gate of the MOS transistor, said protection diode being formed directly below said gate insulating layer such that said protection diode is formed integrally as part of the MOS transistor; wherein excess charge buildup in the MOS transistor is conducted through said gate conductive layer and away from the MOS transistor by said protection diode.

Claim 11

A process for fabricating a MOS transistor according to claim 8, wherein said layer of insulating material comprises oxide.

Claim 12

A process for fabricating a MOS transistor according to claim 8, wherein said layer of insulating material comprises nitride.

Claim 13

A process for fabricating a MOS transistor according to claim 8, wherein said layer of insulating material comprises oxide and nitride.

Claim 14

A process for fabricating a MOS transistor according to claim 8, wherein said layer of conductive material comprises polysilicon.

Claim 15

A process for fabricating a MOS transistor according to claim 8, wherein said layer of conductive material comprises metal.

Claim 16

A process for fabricating a MOS transistor according to claim 8, wherein said layer of conductive material comprises single crystal silicon.

Claim 17

A process for fabricating a MOS transistor according to claim 8, wherein said protection diode is formed in said tie-down region by out-diffusion.

Claim 18

A process for fabricating a MOS transistor according to claim 8, wherein said protection diode is formed in said tie-down region by ion implantation.

Claim 19

A process for fabricating a MOS transistor according to claim 8, wherein the MOS transistor is a NMOS transistor.

Claim 20

A process for fabricating a MOS transistor according to claim 8, wherein the MOS transistor is a PMOS transistor.

Claim 21

A process for fabricating a MOS transistor according to claim 8, further comprising the step of depositing a protective layer on said layer of insulating material prior to said step of forming a buried protection diode window, said protective layer protecting said layer of insulating material from contamination during processing.

Claim 22

A process for fabricating a MOS transistor according to claim 19, wherein said protective layer comprises polysilicon.

Claim 23

A process for fabricating a MOS transistor according to claim 8, wherein said layer of insulating material has a thickness of less than 100 Angstroms.

Claim 24

A process for fabricating a MOS transistor according to claim 8, wherein the process is implemented in a BiCMOS technology, wherein said layer of conductive material of the MOS transistor comprises the same material used to form a base of a bipolar transistor, and wherein said buried protection diode window and an opening for the base of the bipolar transistor are formed in one process step.

Claim 25

A process for fabricating a MOS transistor according to claim 8, wherein the process is implemented in a BiCMOS technology, wherein said layer of conductive material of the MOS transistor comprises the same material used to form an emitter of a bipolar transistor, and wherein said buried protection diode window and an opening for the emitter of the bipolar transistor are formed in one process step.