MOS power structure with protective device against overvoltages and manufacturing process therefor

Claim 1

A method of fabricating a MOS power structure comprising the steps of: (a) forming a N - -doped epitaxial layer on a N + -doped semiconductor substrate; (b) forming an oxide layer on the epitaxial layer; (c) patterning the oxide layer to form windows corresponding to the well regions of MOS cells and the base region of a bipolar transistor protection structure; (d) implanting acceptor impurities through the patterned oxide layer to simultaneously form the p + -well regions and the p + -base region; (e) depositing a gate oxide layer on the entire surface of the epitaxial layer; (f) depositing a polysilicon gate electrode layer on the oxide layer; (g) patterning the polysilicon layer to form gate electrode regions for the MOS cells; (h) implanting acceptor impurities into the epitaxial layer using the gate electrode regions as a mask to form the p - -channel regions which control the threshold of the MOS cell; (i) forming a second oxide pattern corresponding to the source regions of the MOS cells and the emitter region of the protection device; (j) implanting donor impurities into the p + -well regions and the p + -base region of the protection device to simultaneously form the N + -source regions of the MOS cells and the N + -emitter region of the bipolar protection device; (k) forming a third oxide pattern corresponding to ohmic contacts; and (l) depositing a metallization layer connecting between the source electrode and the well region of each MOS cell and the base region of the protection transistor and a metallization layer connecting the gate of the MOS cell to the emitter region of the protection transistor.

Claim 2

A method of fabricating a MOS power structure comprising the steps of: (a) forming a N - -doped epitaxial layer on a N + -doped semiconductor substrate; (b) forming an oxide layer on the epitaxial layer; (c) patterning the oxide layer to form windows corresponding to the well regions of MOS cells and the base region of a bipolar transistor protection structure; (d) implanting acceptor impurities through the patterned oxide layer to simultaneously form the p + -well regions and the p + -base region; (e) depositing a gate oxide layer on the entire surface of the epitaxial layer; (f) depositing a polysilicon gate electrode layer on the oxide layer; (g) patterning the polysilicon layer to form gate electrode regions for the MOS cells; (h) implanting acceptor impurities into the epitaxial layer using the gate electrode regions as a mask to form the p - -channel regions which control the threshold of the MOS cell; (i) forming a second oxide pattern corresponding to the source regions of the MOS cells and the emitter region of the protection device; (j) implanting donor impurities into the p + -well regions and the p + -base region of the protection device to simultaneously form the N + -source regions of the MOS cells and the N + -emitter region of the bipolar protection device; (k) forming a third oxide pattern corresponding to ohmic contacts; and (l) depositing a metallization layer connecting between the source electrode and the well region of each MOS cell and the base region of the protection transistor and a metallization layer connecting the gate of the MOS cell to the emitter region of the protection transistor.

Claim 3

A method of fabricating a MOS power structure comprising the steps of: (a) forming a N - -doped epitaxial layer on a N + -doped semiconductor substrate; (b) forming an oxide layer on the epitaxial layer; (c) patterning the oxide layer to form a window corresponding to the anode region of a zener diode; (d) implanting acceptor impurities through the patterned oxide layer to form the p + -anode region of the zener diode at a specified depth; (e) forming and patterning a second oxide layer to establish windows corresponding to the well regions of MOS cells and the base region of a bipolar transistor protection structure; (f) implanting acceptor impurities through the patterned oxide layer to simultaneously form the p + -well regions and the p + -base region in the epitaxial layer; (g) depositing a gate oxide layer on the entire surface of the epitaxial layer; (h) depositing a polysilicon gate electrode layer on the oxide layer; (i) patterning the polysilicon layer to form gate electrode regions for the MOS cells; (j) implanting acceptor impurities into the epitaxial layer using the gate electrode regions as a mask to form the p - -channel regions which control the threshold of the MOS cells; (k) forming a third oxide pattern corresponding to the source regions of the MOS cells and the emitter region of the bipolar transistor protection structure; (l) implanting donor impurities into the p + -well regions and the p + -base region of the bipolar protection device to simultaneously form the N + -source regions of the MOS cells and the N + -emitter region of the bipolar transistor protection structure; (m) forming a fourth oxide pattern corresponding to ohmic contacts; and (n) depositing a metallization layer connecting between the source electrode and the well region of each MOS cell and the base region of the protection transistor as well as the anode region of the zener diode and a metallization layer connecting the gate of the MOS cell to the emitter region of the bipolar transistor protection structure.

Claim 4

A method of fabricating a MOS power structure comprising the steps of: (a) forming a N - -doped epitaxial layer on a N + -doped semiconductor substrate; (b) forming an oxide layer on the epitaxial layer; (c) patterning the oxide layer to form a window corresponding to the anode region of a zener diode; (d) implanting acceptor impurities through the patterned oxide layer to form the p + -anode region of the zener diode at a specified depth; (e) forming and patterning a second oxide layer to establish windows corresponding to the well regions of MOS cells and the base region of a bipolar transistor protection structure; (f) implanting acceptor impurities through the patterned oxide layer to simultaneously form the p + -well regions and the p + -base region in the epitaxial layer; (g) depositing a gate oxide layer on the entire surface of the epitaxial layer; (h) depositing a polysilicon gate electrode layer on the oxide layer; (i) patterning the polysilicon layer to form gate electrode regions for the MOS cells; (j) implanting acceptor impurities into the epitaxial layer using the gate electrode regions as a mask to form the p - -channel regions which control the threshold of the MOS cells; (k) forming a third oxide pattern corresponding to the source regions of the MOS cells and the emitter region of the bipolar transistor protection structure; (l) implanting donor impurities into the p + -well regions and the p + -base region of the bipolar protection device to simultaneously form the N + -source regions of the MOS cells and the N + -emitter region of the bipolar transistor protection structure; (m) forming a fourth oxide pattern corresponding to ohmic contacts; and (n) depositing a metallization layer connecting between the source electrode and the well region of each MOS cell and the base region of the protection transistor as well as the anode region of the zener diode and a metallization layer connecting the gate of the MOS cell to the emitter region of the bipolar transistor protection structure.