EP0065269A2
Expired / Lapsed
EP
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Switching device and circuit
Assignee: Hitachi Ltd
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Filing: 1982-05-12
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Granted: —
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Expires: 2002-05-12
Abstract
Abstract A switching device and circuit comprises a bi-polar transistor (3, 3') and at least two field effect transistors (1, 2, 24, 30) for controlling the bi-polar transistor. A first field effect transistor (1, 30) has its drain and source connected across the collector-base of the bi-polar transistor and a second field effect transistor (2, 24) has its drain and source connected across the base-emitter of the bi-polar transistor. Gates of the first and second field effect transistors are connected in common and applied with a voltage signal. The first field effect transistor (1, 30) is of an enhancement type and the second field effect transistor (2, 24) is of a depletion type.
Inventors
- 👤 Takao Sasayama
- 👤 Kazuo Kato
- 👤 Masayoshi Naito
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 18:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H10D84/80; H10D84/82; H10D84/83; H10D84/8311
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A switching device comprising a MOS FET(1), a depletion type FET (24) and a bi-polar transistor (3) a source of the MOS FET being connected to a drain of the depletion type FET with the connecting junction connected to a base of the bi-polar transistor, a drain of the MOS FET being connected to a collector of the bi-polar transistor and a source of the depletion type FET being connected to an emitter of the bi-polar transistor, the collector-emitter conduction or non-conduction of said bi-polar transistor being controlled by an input signal applied to gates of the MOS FET and depletion type FET connected in common.
Claim 2
Dependent Claim
106 words
A switching device comprising a MOS FET(1), a depletion type FET (24) and a bi-polar transistor (3) a source of the MOS FET being connected to a drain of the depletion type FET with the connecting junction connected to a base of the bi-polar transistor, a drain of the MOS FET being connected to a collector of the bi-polar transistor and a source of the depletion type FET being connected to an emitter of the bi-polar transistor, the collector-emitter conduction or non-conduction of said bi-polar transistor being controlled by an input signal applied to gates of the MOS FET and depletion type FET connected in common.
Claim 3
Dependent Claim
26 words
A switching device according to claim 1, wherein the MOS FET (1) and depletion type FET (24) have carrier polarities which are different from each other.
Claim 4
Dependent Claim
56 words
A switching device according to claim 1, wherein a collector layer of the bi-polar transistor(3) and a drain layer of an enhancement type MOS FET (30) are formed in common, and the depletion type FET (24)in the form of a junction type FET which is insulated by an isolation layer is formed in the common layer.
Claim 5
Dependent Claim
66 words
A switching device according to claim 1 as illustrated in Figs. 7 and 8, wherein a collector layer of the bi-polar transistor (30) and a drain layer of an enhancement type MOS FET (30) are formed in common, and the depletion type MOS FET (24) in the form of a depletion type FET is formed which has a channel between emitters formed in the common layer.
Claim 6
Dependent Claim
34 words
A switching device according to claim 1, wherein a metal-semiconductor diode is connected across the base-collector of said bi-polar transistor (3), said diode having the same rectifying direction as that of the base-collector junction.
Claim 7
Dependent Claim
86 words
A circuit incorporating the switching device according to claim 1 as illustrated in Fig. 9, wherein a source of an enhancement type FET having the same polarity as that of an enhancement type MOS FET (30) connected across the collector-base of a bi-polar (3') transistor is connected to a base electrode of the bi-polar transistor, gates of the enhancement type MOS FET and the enhancement type FET are connected in common, and a drain of the enhancement type FET is connected to a bias supply source.
Claim 8
Dependent Claim
27 words
A circuit incorporating the switching device according to claim 1 as illustrated in Fig. 10, wherein said circuit is directly driven by a CMOS timer PWM circuit
References Cited (Backward Citations)
No citation records indexed.
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