MOS transistor

Claim 2

A vertical MOS transistor comprising: a low specific resistance drain region of a first conductivity type provided with a drain electrode on a lower surface thereof, a high specific resistance drain region of said first conductivity type located on an upper surface of said low specific resistance drain region, a diffused well region of a second conductivity type having a lower surface in contact with said upper surface of said low resistivity drain region to form a junction, said well region having a lower impurity concentration than said low resistivity drain region; a source region of said first conductivity type partially surrounded by said well region and provided with a source electrode, means for directly electrically connecting said well region to the source electrode; and a gate electrode formed above the surface of said well region on an insulating layer; so that a wide zener diode is formed along said junction between said lower surface of said well region and said upper surface of said low specific resistance drain region and a breakdown voltage applied across said source and drain electrode causes a uniform flow of breakdown current across said junction.

Claim 3

A vertical MOS transistor according to claim 1, wherein said well region includes lateral surfaces in contact with said high specific resistance drain region.

Claim 4

A vertical MOS transistor according to claim 1, comprising a plurality of similar cells, each of said cells comprising said low specific resistance drain region, said high specific resistance drain region, said well region, said source region, and said gate region so that said wide zener diode is formed in each cell, said cells being connected in parallel.

Claim 5

A vertical MOS transistor according to claim 1, wherein said gate electrode extends over both said source regions and said high specific resistance drain region.

Claim 6

A vertical MOS transistor according to claim 1, wherein said upper surface of said low specific resistance drain region is flat and said lower surface of said well region is flat.

Claim 7

A vertical MOS transistor according to claim 1, wherein said means comprises a low specific resistance contact region formed in said well region.

Claim 8

A vertical MOS transistor according to claim 3, wherein said well regions are formed by diffusion.

Claim 9

A vertical MOS transistor according to claim 7, wherein said well regions have a specific resistance between said high specific resistance drain regions and said low specific resistance drain regions.

Claim 10

A vertical MOS transistor according to claim 2, wherein said lateral surfaces include convexly curved portions.

Claim 13

A device as set forth in claim 10, wherein said well region has a resistivity between that of said high resistivity region and that of said low resistivity region.

Claim 14

A device as set forth in claim 11, wherein said means comprises a low resistivity region formed in said well region.

Claim 15

A device as set forth in claim 12, wherein said lateral surfaces include convexly curved portions.

Claim 16

A vertical MOS transistor comprising: a low specific resistance region of a first conductivity type provided with a drain electrode on a lower flat surface thereof, a high specific resistance region of said first conductivity type located on a first portion of an upper surface of said low specific resistance region, a well region of a second conductivity type opposite said first conductivity type located side by side with said high specific resistance region, a source region of said first conductivity type formed in said well region and provided with a source electrode, a gate electrode formed on an upper surface of said well region through an insulating layer and extending over both of said source region and said high specific resistance region, and means for forming a wide channel zener diode between the source electrode and the drain electrode, said means including a buried region of said second conductivity type having an impurity concentration higher than that of said well region and disposed between a bottom surface of said well region and a second portion of said upper surface of said low specific resistance region, said diode being formed along a lower surface of said buried region adjoining said second portion of said upper surface of said low specific resistance region.

Claim 17

A vertical MOS transistor comprising: a low specific resistance region of a first conductivity type provided with a drain electrode on a lower flat surface thereof, a high specific resistance region of said first conductivity type located on a first portion of an upper surface of said low specific resistance region, a well region of a second conductivity type opposite said first conductivity type located side by side with said high specific resistance region, a source region of said first conductivity type formed in said well region and provided with a source electrode, a gate electrode formed on an upper surface of said well region through an insulating layer and extending over both of said source region and said high specific resistance region, and means for forming a wide channel zener diode between the source electrode and the drain electrode, said means including a buried region of said second conductivity type having an impurity concentration higher than that of said well region and disposed between a bottom surface of said well region and a second portion of said upper surface of said low specific resistance region, said diode being formed along a lower surface of said buried region adjoining said second portion of said upper surface of said low specific resistance region.

Claim 18

A vertical MOS transistor claimed in claim 6, wherein, said first conductivity type is an N type conductivity.

Claim 19

A vertical MOS transistor as claimed in claim 14, wherein said high specific resistance region, said well region, said source region, and said buried region are diffused regions.

Claim 20

A vertical MOS transistor comprising: a semiconductor substrate of a first conductivity type provided with a drain electrode on a lower surface thereof, a well region of a second conductivity type opposite said first conductivity type formed in an upper portion of said substrate, a source region of said first conductivity type having a source electrode and being formed in said well region, and a gate electrode formed on the surface of said well region through an insulating layer, means for forming a wide channel zener diode between said source electrode and said drain electrode, said means including a low specific resistance region of said first conductivity type disposed between a bottom surface of said well region and said substrate, said diode being formed along an elongated substantially planar interface of said low spacific resistance region and substrate.

Claim 21

A vertical MOS transistor comprising: a semiconductor substrate of a first conductivity type provided with a drain electrode on a lower surface thereof, a well region of a second conductivity type opposite said first conductivity type formed in an upper portion of said substrate, a source region of said first conductivity type having a source electrode and being formed in said well region, and a gate electrode formed on the surface of said well region through an insulating layer, means for forming a wide channel zener diode between said source electrode and said drain electrode, said means including a low specific resistance region of said first conductivity type disposed between a bottom surface of said well region and said substrate, said diode being formed along an elongated substantially planar interface of said low spacific resistance region and substrate.